2026 IEEE/JSAP Symposium on VLSI Technology & Circuits
2026 IEEE/JSAP Symposium on VLSI Technology & Circuits
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Zhengya Zhang

Posted December 1, 2021 by vlsidev_qn81ur & filed under Circuits Papers.

Recipient: Zhengya Zhang

Paper: A 47 Gb/s LDPC Decoder with Improved Low Error Rate Performance

Authors: Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolic

Affiliation: University of California, Berkeley, USA

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