The VLSI Workshop sessions are key elements of the 2022 IEEE Symposium on VLSI Technology & Circuits program. The Workshop sessions will be held during the VLSI Symposium in person and available for on demand viewing. The topics and scope of the Workshops are merging research and application, which has not been covered in detail in the technical program of the symposium and could be the future new areas of the symposium. 

Thursday, June 16 – 8:00 p.m. – 10:00 p.m.

Technology Workshop 1 – Honolulu 1

8:00 PM – 10:00 PM

Machine Learning Applications in Semiconductor Processes and Equipment Development (can the remaining information be in accordion so the other 4 workshops aren’t lost?)

Machine learning has taken the forefront as the newest set of computational and analytical tools that can utilize large amounts of data and output patterns, solutions, diagnostics, and warnings, to enhance human decision making for the purposes of improving semiconductor process development and manufacturing. This workshop aims to highlight select applications, such as metrology, end-point detection, defect analysis, and plasma process development that have recently integrated Machine Learning and Artificial Intelligence as part of the semiconductor fabrication tool-set.


Monica Titus, Technologist R&D Engineering, Western Digital Corporation

Raghuveer Makala, Director R&D Engineering, Western Digital Corporation


  • Machine Learning for Wafer Monitoring and Plasma Process End-Point Detection
  • Machine Learning for Plasma Characterization and Modeling of RIE systems
  • Machine Learning for Metrology/Failure Analysis/Diagnostics
  • Machine Learning for Tool/Fab/Predictive Maintenance


  • Active Learning for Optimal Design of Experiments with Multiple Objectives for Non-equilibrium Plasma Processes
    • Dr. Ali Mesbah, UC Berkeley     
  • Application of Contrastive Representation Learning to Unsupervised Defect Classification in Semiconductor Manufacturing
    • Mr. Shota Mizukami, KIOXIA     
  • Wafer Pattern Recognition for Detecting Process Abnormalities in NAND Flash Memory Manufacturing
    • Ms. Jeongin Choe, Samsung
  • Deep Neural Networks based Image Analysis for Semiconductor Applications
    • Dr. Cheng-Chung Chu, WDC

Technology Workshop 2 – Tapa 1

8:00 PM – 10:00 PM

Heterogenous Integration – The Next Scaling Frontier: Material and Process Challenges


Indira Seshadri, IBM Research

As traditional Moore’s law driven scaling gets slower and more expensive with each node – heterogenous integration (HI) – or the integration of multiple dies in packages provides an alternate opportunity to scale and realize unique architectures. In this workshop, we will first discuss why HI is unique and important starting with a roadmap and high-level design overview session. Enabling HI schemes requires several advancements over traditional packaging technology.   We will follow up the roadmap session with detailed focus talks from leaders in the industry and academia elaborating on some of these unique material and process requirements – hybrid bonding, fan out wafer level packaging, through silicon vias, and thermal management.  We will end with a panel discussion with technology leaders identifying some of the key challenge areas where further advancements are needed to allow HI technology to fully mature.

Heterogenous integration technologies: roadmap, look ahead, key challenges: Device and assembly technologies enabling high performance computing

Speaker: Mustafa Badaroglu

Chip-interconnect technologies and challenges: Hybrid bonding and through silicon via – challenges and opportunities

Speaker: Paul D Franzon

Chip-interconnect technologies and challenges: Reliability Threats of Hybrid Bonding-Based Interconnects; Toward Mass-Production

Speaker: Stephane Moreau

Thermal management of advanced chip stacks: Advanced cooling and design for 2.5D/3D integration

Speaker: Muhannad S Bakir

Joint Workshop Honolulu 2

Cryogenic Electronics for Quantum Computing

8:00 PM – 10:00 PM


Edoardo Charbon, EPFL Switzerland

Bogdan Staszewski, Full Professor, UCD Ireland

Quantum computing has been heralded as a new computation paradigm, capable of solving today’s intractable problems. The core of a quantum computer is a qubit array where superposition, entanglement, and interference are quantum mechanical properties that enable computation. Several styles of qubit have been proposed, while solid-state qubits have recently emerged as the most compelling devices to enable scalable quantum machines.  Nevertheless, solid-state qubits are extremely fragile and generally require cryogenic operation. In this workshop, we look at the control of qubits by way of the most advanced CMOS technologies, which have recently been shown to operate near and below a Kelvin. The presentations will focus on scalability in quantum computing and how cryogenic electronics makes it possible, in principle, to achieve large counts of qubits operating continuously and reliably. The speakers will emphasize these and other aspects of electronic control for solid-state qubits, while introducing a vision for the future.

Si-Spin-Qubit Quantum-Matrix Architecture Requirements

Speaker: Maud Vinet

Distributed Cryogenic CMOS Platform for Autonomous Quantum Control

Speaker: David Reilly

Cryo-CMOS electrical interfaces for large-scale spin-based quantum processors

Speaker: Fabio Sebastiano

Cryo-electronics and system design approaches for superconducting qubit control

Speaker: Kevin Tien

Circuits Workshop 1 – Honolulu 3

Recent Advances in Radar, Mm-Wave, and Sub-THz: Technology, Circuits, and Packaging


This workshop is focused on millimeter-wave radars advancing the role of wireless systems in social infrastructure. We highlight some recently developed systems in a versatile radar application space. Renowned presenters from, both, industry, and academia discuss key technological aspectscircuit design and packaging needed for successful industrialization of modern MMW radar systems



  • A digital-perception radar platform for Automotive Safety
  • Recent Advances in THz Radar Imaging Towards Millimeter Ranging Resolution and 1-Degree 2D Angular Resolution
  • 3D W-band Radar Imaging with Si-based Phased Array Modules

Circuits Workshop 2 – Tapa 2

The Emerging Ecosystem of Open-Source Chip Design


Boris Murmann, Stanford University

Mehdi Saligane, University of Michigan

Open-source development has revolutionized the creation, maintenance, and distribution of software products over the past two decades. In recent years, open source aficionados have set out to replicate this success story for hardware design, including custom VLSI chips. The potential benefits of an open-source ecosystem for chip design are manifold and include: (1) Design re-use and cost-efficient agile design, (2) new opportunities in standardization, crowdsourcing and open global collaboration, (3) democratizing access to chip technology and attracting new talent. The purpose of this workshop is to review the latest developments in this space with a focus on open-source design automation tools and the potential for corporate adoption.

Commercial Open-Source EDA flows and IC design

Speaker: Rob Taylor

Exploring DSA design in RISC-V

Speaker: Chaojun Zhao

The OpenROAD Project: An open-source platform for IC design innovation

Speaker: Andrew Kahng

CHIPKIT: An Agile, reusable open-source framework for rapid test chip development

Speaker: Gu-Yeon Wei

OpenFASOC: Open-Source Fully Autonomous AMS SoC Synthesis

Speaker: David Wentzloff

Panel Discussion on the future of open-source chip design

Speaker: Alessandro Piovaccari

Circuits Workshop 3 – Tapa 3

Analog Circuits for IoT

The semiconductor industry views the emerging Internet of Things (IoT) as a high-volume market for chips. What sets it apart are circuits that consume ultralow power. This is especially a challenge for the analog front ends that condition sensor waveforms. This workshop concerns itself with circuit methods that will prove useful here.


Asad Abidi, UCLA

Christian Enz, EPFL

Case Study of an IoT Power Management System

Speaker: Danielle Griffith

Choice of sensor interface architecture for ultra low-power IoT

Speaker: Ippei Akita

Timekeeping for efficient IoT radio scheduling

Speaker: David Ruffieux

Case study: The Design of an Ultra Low-power SAR ADC

Speaker: Pieter Harpe

On-chip Nanoamp Reference Current Generation

Speaker: Asad Abidi

The specific current extractor circuit for setting the inversion level of a transistor

Speaker: Christian Enz