Media Registration

Registration for the 2022 IEEE Symposium on VLSI Technology & Circuits is complimentary for the media. Details about media registration will be available in March, 2022.

Pre-Publication Guidelines

Prior to the start of the conference, the technical content of press releases regarding accepted papers must be limited to information included in the Symposium Advance Program or the Symposium Press Kit. After this date, press releases on the technical content of the full accepted papers are allowed.

Online Media Briefing

The Symposium organizers are planning an online briefing for the media to discuss the most newsworthy papers and major technology trends in this year’s Symposium program. Details will be available in April 2022.

Media Contacts

NORTH AMERICAN & EU
BTB Integrated Marketing –
Chris Burke, co-Media Relations Director

E-mail: chris.burke@btbmarketing.com


JAPAN & ASIA
Secretariat for VLSI Symposia c/o JTB Communication Design, Inc. Tokyo, Japan

E-mail: vlsisymp@jtbcom.co.jp


2022 IEEE Symposium on VLSI Technology & Circuits Media Kit

Welcome to the Media Center for the Symposium. The following press materials may be downloaded for news coverage of the 2022 IEEE Symposium on VLSI Technology & Circuits.


2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY NEWS RELEASES:

2022 IEEE Symposium on VLSI Technology & Circuits

2022 VLSI Call for Workshops News Release

2022 VLSI Call for Papers News Release

2022 IEEE VLSI Symposium Logo

Honolulu, Hawaii Image


2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY IMAGES AND CAPTIONS:

Selected images from the highlighted papers are presented in two formats:

  • Word file with embedded image and caption
  • JPEG file of individual high-resolution images

Session JFS4-2: “A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation Between Sub-arrays” – Georgia Institute of Technology

Session T1-3: “A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency” – Sony

Session C22-1: “Fully Integrated Voltage Regulators with Package-Embedded Inductors for Heterogeneous 3D-TSV-Stacked System-in-Package with 22nm CMOS Active Silicon Interposer Featuring Self-Trimmed, Digitally Controlled ON-Time Discontinuous Conduction Mode (DCM) Operation” – Intel

Session C24-3: “Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications” – Meta

Session C15-1: “A 16GB 1024GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features” – Samsung

Session C5-2: “A Hybrid Indirect ToF Image Sensor for Long-Range 3D Depth Measurement Under High Ambient Light Conditions” – Toppan Inc.

Session C19-1: “An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class‑AB Buffer in 4nm CMOS” – IBM Research, Switzerland

Session JCS1-2: “Scalable 1.4μW cryo-CMOS SP4T Multiplexer Operating at 10mK for High-Fidelity Superconducting Qubit Measurements” – KU Leuven

Session C3-2: “A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links” – IBM Research, USA

Session C2-1: “A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm” – NVIDIA

Session C9-2: “1200×84-pixels 30fps 64cc Solid-State LiDAR RX with a HV/LV Transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation” – Toshiba

Session C21-4: “A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications” – Samsung

Session T1-4: “Reliable Sub-nanosecond MRAM with Double Spin-Torque Magnetic Tunnel Junctions” – IBM

Session C11-2: “A 39GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-Station” – Tokyo Institute of Technology

Session T4-1: “First Demonstration of Ge2Sb2Te5-Based Superlattice Phase Change Memory with Low Reset Current Density (~3 MA/cm2) and Low Resistance Drift (~0.002 at 105ºC)” – Stanford University

Session T1-2: “Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails” – imec

Session JFS4-1: “An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine” – University of Michigan

Session T15-4: “Low-capacitance Ultrathin InGaAs Membrane Photodetector on Si Slot Waveguide towards Receiver-less System” – The University of Tokyo

Session C25-1: “Experimental Demonstration of Novel Scheme of HZO/Si FeFET Reservoir Computing with Parallel Data Processing for Speech Recognition” – The University of Tokyo

Session T1-5: “Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor” – TSMC 

Session C24-1: “Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology” – Intel

Session T15-2: “First Monolithic Integration of Group IV Waveguide Photodetectors and Modulators on 300mm Si Substrates for 2μm Wavelength Optoelectronic Integrated Circuit” – University of Singapore 

Session T8-4: “A 0.6µm Small Pixel for High Resolution CMOS Image Sensor with Full Well Capacity of 10,000e- by Dual Vertical Transfer Gate Technology” – Samsung 

Session T2-3: “Vertical Channel-All-Around (CAA) IGZO FET less than 50nm CD with High Read Current of 32.8μA/μm (Vth + 1V), Well-Performed Thermal Stability up to 120°C for Low Latency, High-Density 2T0C 3D DRAM Application” – Huawei 

Session T1-1: “Intel 4 CMOS Technology Featuring Advanced FinFET Transistors Optimized for High Density and High-Performance Computing” – Intel

Session C11-4: “An Ultra-Compact Bidirectional T/R Folded 25.8-39.2GHz Phased-Array Transceiver Front-End with Embedded TX Power Detection/Self-calibration Path Supporting 64/256/512QAM at 28/39GHz band for 5G in 65nm CMOS Technology” – Tsinghua University