C. Patrick Yue and S. Simon Wong, “On-Chip Spiral Inductors with Patterned Ground Shields
for Si-Based RF IC’s
”,  Sump. VLSI Circuits, Paper 12-1, pp. 85-86 (1997).

C. Patrick Yue (eepatrick@ust.hk)


This paper in 1997 introduced the first on-chip inductor with a patterned ground shield(PGS) inserted between the spiral inductor and the silicon substrate. PGS’s were realized in standard CMOS technologies using poly-silicon layer without additional processing steps – this was a key factor that drives its adoption and proliferation in low cost RFIC’s. PGS’s increase the inductor quality factor, reduce the substrate noise coupling, and improve the inductor model accuracy by decoupling the lossy silicon substrate. Over the years, PGS’s have become a de facto feature for on-chip inductors and are widely adopted.

Leland Chang, David M. Fried, Jack Hergenrother, Jeffrey W. Sleight, Robert H. Dennard, Robert K. Montoye, Lidija Sekaric, Sharee J. McNab, Anna W. Topol, Charlotte D. Adams, Kathryn W. Guarini, and Wilfried Haensch, ” Stable SRAM Cell Design for the 32 nm Node and Beyond,” Symp. VLSI Technology, paper 8A-2, pp. 128-129 (2005).

Leland Chang (lelandc@us.ibm.com)


This paper in 2005 introduced the first publication of an 8T-SRAM cell with separate read stack, enables

stability for future technologies due to variability and decreasing power supply voltages. The proposed 8T-SRAM provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling.  This cell is widely used in high-speed applications today and is a standard offering of foundries in advanced technology nodes.