Technology
C. Auth; A. Cappellani; J.-S. Chun; A. Dalis; A. Davis; T. Ghani; G. Glass; T. Glassman; M. Harper; M. Hattendorf; P. Hentges; S. Jaloviar; S. Joshi; J. Klaus; K. Kuhn; D. Lavric; M. Lu; H. Mariappan; K. Mistry; B. Norris; N. Rahhal-orabi; P. Ranade; J. Sandford; L. Shifren; V. Souw; K. Tone; F. Tambwe; A. Thompson; D. Towner; T. Troeger; P. Vandervoorn; C. Wallace; J. Wiedemer; C. Wiegand
Intel Corporation
Paper: 45nm High-k + metal gate strain-enhanced transistors, (2008 Symposium on VLSI Technology, pp. 128-129, paper 13-2)
Citation:
This paper showed for the first time the enhancement of strain and performance when using techniques such as embedded SiGe, gate fill stress and trench contacts with Gate Last high-ĸ/metal gate planar technology including. These techniques continued to be utilized through the FinFET era
Circuits
A. M. Abo; P. R. Gray
University of California, Berkeley
Paper: A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter, (1998 Symposium on VLSI Circuits, pp. 166-169, paper 14-2)
Citation:
This paper introduced the first bootstrapped switch that does not present overvoltage stress on any transistor, extending high linearity switched capacitor techniques into the submicron and deep submicron CMOS era. Bootstrapping uses a constant gate-to-source voltage across the sampling transistor to improve linearity and signal fidelity. The gate voltage tracks the input and exceeds the power supply voltage. This paper uses a voltage doubler and appropriate clocking and stacking to preserve reliability and has become a standard sampling circuit ever since.
