Technology Short Courses: Technologies Shaping the Future as Key Enablers for AI
| Start | End | Agenda |
| 8:30 | 8:35 | Opening (5 min) |
| 8:35 | 9:25 | Advanced Logic Scaling, Dechao Guo, IBM |
| 9:25 | 10:15 | DTCO Logic, Functional BS, Thermal and Power Delivery, STCO Logic + Memory, Dwaipayan Biswa, imec |
| 10:15 | 10:35 | Break (20 min) |
| 10:35 | 11:25 | Heterogenous/3D Integration, Chih Hang Tung, TSMC |
| 11:25 | 12:15 | Processes for Logic and Memory, Milan Pesic, AMAT |
| 12:15 | 1:15 | Lunch (60 min) |
| 1:15 | 2:05 | Advanced DRAM Technology, Jin-Woo Han, Samsung |
| 2:05 | 2:55 | Emerging Memories, Masatoshi Yoshikawa, KIOXIA |
| 2:55 | 3:15 | Break (20 min) |
| 3:15 | 4:05 | Oxide Semiconductors for Logic and Memory Applications, Gong Xiao, NUS |
| 4:05 | 4:55 | Si Photonics as Enabler for Advanced Optical Interconnects for AI, HP Computing, Ben Lee, NVIDIA |
| 4:55 | 5:00 | Closing (5 min) |
Circuits Short Courses: AI-Driven Design Acceleration: Learning Across Circuits, Technology, and Yield
| Start | End | Agenda |
| 8:30 | 8:35 | Opening (5 min) |
| 8:35 | 9:25 | Opportunities and Challenges of AI in Circuit Design Boris Murmann, University of Hawaii |
| 9:25 | 10:15 | Generative AI for Design Automation & System Integration, Erick Chao, Siemens |
| 10:15 | 10:35 | Break (20 min) |
| 10:35 | 11:25 | Machine Learning and Convex Optimization to Improve Chip Design Quality and Productivity Tai-Lai Tung, MediaTek |
| 11:25 | 12:15 | AI-Enhanced analog/mixed-signal/mmWave IC Design Mike Shuo-Wei Chen, USC |
| 12:15 | 1:15 | Lunch (60 min) |
| 1:15 | 2:05 | Learning from Silicon: AI for Validation, Test, and Yield Improvement Piyushv Verma, Synopsys |
| 2:05 | 2:55 | AI Models for Yield Improvements, Koki Tsurusaki, Rapidus |
| 2:55 | 3:15 | Break (20 min) |
| 3:15 | 4:05 | Advanced AI-driven Design Methodologies for Memory Interfaces, Aman Joshi, SanDisk |
| 4:05 | 4:55 | AI for Memory and Storage Circuit Optimization, Tsung-Yung Jonathan Chang, TSMC |
| 4:55 | 5:00 | Closing (5 min) |
