2026 Plenary Sessions

Building the Engine of AI: From Foundational VLSI Technologies to System-Scale Impact

AI is reshaping our lives. New models demonstrate increasing levels of intelligence in applications ranging from entertainment to productivity to scientific discovery. This impact is profound and accelerating, but the frontier-scale training and inference-demands this creates is placing unprecedented stress on every layer of hardware systems.

For AI to serve all of humanity, we must solve these hardware challenges at scale to overcome bottlenecks in compute, memory bandwidth, connectivity, and physical datacenter infrastructure.

Progress will not come from transistor scaling alone; it will require advances in circuits and technologies for memory integration, low-power interconnect, power delivery, thermals, and advanced packaging. These innovations must be co-optimized within a coherent system architecture. Only through holistic, system-level innovation—paired with disciplined execution—can we achieve the perf/watt and perf/TCO improvements needed to make AI’s benefits broadly accessible.

Dr. Richard Ho

Head of Hardware
OpenAI

Richard Ho leads Hardware at OpenAI, where he focuses on co-optimizing large-scale compute systems with the machine-learning models that power modern AI. Previously, he helped start and then led Google’s TPU program across multiple generations and was a core contributor to D. E. Shaw Research’s Anton supercomputers for molecular dynamics simulation. Earlier in his career, he co-founded 0-In Design Automation, a pioneer in chip-verification tools later acquired by Mentor Graphics (now Siemens). Richard holds a Ph.D. in Computer Science from Stanford University and M.Eng. and B.Sc. degrees in Microelectronic Systems Engineering from the University of Manchester.

Advanced Package for Next-Generation AI System Scaling

Advanced packages have emerged as the pivotal technology for next-generation AI system scaling to meet demanding performance, power efficiency, and bandwidth requirements. As compute density increases, the growing need for communication bandwidth reaches the highest priority. We will first present continuous UCIe bandwidth increase through the advancements in 2.5D package. Next, we will illustrate silicon photonics innovations, addressing communication energy efficiency and system-level interconnect challenges within the AI datacenter. As multi-layer 3D stacking for silicon, memory and package becomes the mainstream integration, thermal and power supply become the key limiters on performance. We will present the thermal optimization for 3D stacking integration to address the cooling needs, as well as the vertical power delivery network (PDN) used to reduce IR drop and improve power efficiency. Finally, we will report the key highlights of 3Dblox’s crucial role in the design industry, enabling 3DIC design interoperability and heterogeneous multi-die automation, as it actively undergoes IEEE standardization.

Dr. L.C. Lu

Senior Fellow and Vice President, Research & Development / Design & Technology Platform, TSMC

L.C. Lu is Vice President of Research & Development / Design & Technology Platform at TSMC and a TSMC Senior Fellow. Dr. Lu is responsible for supporting design enablement to meet a wide range of requirements from TSMC’s broad customer base. Dr. Lu collaborated with TSMC process RD to innovate Design and Technology Co-Optimization (DTCO) to enhance speed, power and density for TSMC’s advanced process technologies. He has worked closely with design ecosystem partners through the TSMC Open Innovation Platform® (OIP) to provide comprehensive design solutions and IPs to enable many different customer applications. Dr. Lu is one of TSMC’s most prolific inventors with more than 200 patents in the United States and other countries. Dr. Lu received his B.S. in Electrical Engineering from National Taiwan University, M.S. in Computer Science from National Tsing Hua University, and Ph.D. in Computer Science from Yale University.

Intelligence Accelerated: Memory Innovations to Power the AI Era

Artificial intelligence is driving exponential growth in computation, data transfer, and energy consumption. As model sizes surpass the trillion-parameter threshold and reasoning workloads increase demands on bandwidth and latency, memory has emerged as the central constraint for advanced AI systems rather than compute resources. Meeting these exponential requirements necessitates coordinated advancements in memory technologies—such as DRAM and NAND, high-bandwidth memory, and packaging solutions including hybrid bonding, fine-pitch die-to-die interconnects, and vertically stacked memory architectures. Breakthroughs in materials science, sophisticated physics-based modeling, wafer bonding, and advanced metrology solutions are essential for rapid progress. The integration of emerging non-volatile memories and CXL-enabled expansion frameworks further supports heterogeneous and composable memory systems tailored for large-scale AI. This work outlines device, packaging, energy-efficiency, and memory product innovations required to address the evolving needs of AI workloads over the next decade.

Dr. Nirmal Ramaswamy

Corporate Vice President, Micron Technology

Nirmal Ramaswamy is currently the Corporate Vice President of DRAM Technology Group at Micron Technology Inc. He has a bachelor’s degree in metallurgical engineering from Indian Institute of Technology, Madras, India, a PhD in Materials Science and Engineering from Arizona State University and is a graduate of the Stanford Graduate School of Business – Executive Program. Since joining Micron in 2002, Dr. Ramaswamy has held numerous leadership positions across process development, process integration, and technology development for DRAM, NAND, and emerging memory technologies. He holds more than 350 issued patents in the field of semiconductors and has authored more than 30 technical papers.

Meeting AI Demand Through Equipment Innovation and AI-Driven Manufacturing: Progress and Challenges 

Our industry has grown together with the evolution of semiconductor manufacturing equipment. Driven by the rise of AI and its prospects , the role of semiconductors continues to expand, and equipment has become even more critical. At the same time, it is increasingly important to apply AI to equipment technologies and fab operations themselves. In this talk, we will present our efforts on both fronts. 

We will introduce how new equipment and process technologies contribute to the advancement of AI systems toward more high performance with less power consumption, and how we are using AI in equipment and fab technology. 

We will outline current progress, challenges, and next steps. By addressing these two sides together, we aim to show how the semiconductor industry can meet the needs of AI today and in the future.

Mr. Yoshinobu Mitano

VP Corporate Innovation Division, Tokyo Electron Ltd

Mr. Yoshinobu Mitano leads the business and the innovation of wafer fabrication equipment of Tokyo Electron Limited as Corporate Officer and EVP & GM of Corporate Innovation Division. He graduated from Keio University in March 1985 and joined Tokyo Electron Limited in April 1985, where he was assigned to the Device Design Center. In April 1989 he became an Etch Field Engineer, and in April 1990 he served as an Etch Field Engineer in Italy. In August 1992 he moved to Etch Marketing at Tokyo Electron Limited, and in April 1993 he continued Etcher Marketing at Tokyo Electron America, Inc.
In January 1995 he joined the Etch Systems Department, and in October 1996 he again worked in the Etch Systems Department at Tokyo Electron America, Inc. In May 1998 he was assigned to the Etch Systems Business Unit, and in April 2003 he was appointed Director of the Etch Systems Business Unit. In October 2008 he participated in the 3DI project, and in July 2012 he became Vice President and General Manager of the 3DI Division.
In February 2013 he was appointed Vice President and Deputy General Manager of the Etch Systems Business Unit, and in June 2017 he was promoted to Senior Vice President and Deputy General Manager of the Etch Systems Business Unit. In July 2018 he served as Senior Vice President and General Manager of the SPE Business Division. In June 2019 he was elected to the Board of Directors of Tokyo Electron.
Subsequently, in July 2022 he became a Corporate Officer serving as Executive Vice President and General Manager of the SPE Business Division, and in July 2024 he assumed the role of Corporate Officer, Executive Vice President and General Manager of the Corporate Innovation Division.