Yoshinobu Nakagome, Yoshifumi Kawamoto, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, and Kiyoo Itoh, “A. 1.5V Circuit Technology for 64Mb DRAMs”, Symp. VLSI Circuits, paper 2-5, pp. 17-18 (1990).
This paper in 1990 introduced the idea of doubling the supply voltage through on-chip capacitive charge-pump circuit to boost the gate voltage of MOS switch to increase the turn-on voltage to effectively reduce its on-resistance for low voltage DRAM applications. Many variations of switch boosters followed this paper which formed an important foundation in today’s high performance switch capacitor circuits.
Jack Kavalieros, Brian Doyle, Suman Datta, Gilbert Dewey, Mark Doczy, Ben Jin, Dan Lionberger, Matthew Metz, Willy Rachmady, Marko Radosavljevic, Uday Shah, Nancy Zelick, Robert Chau, ”Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering,” Symp. VLSI Technology, paper 7-1, pp. 50-51 (2006).
Strained silicon and high-k gate dielectrics with metal gates were introduced to high volume manufacturing in 2003 and 2007 respectively, while FinFETs were still the subject of research at that time. This pioneering work in 2006 was the first demonstration of FinFETs combined with the other two boosters – uniaxial strained silicon and high-k/metal gate, a combination that would later dominate the industry.
Hiroyasu Tanaka, Masaru Kidoh, Katsunori Yahashi, Mitsuhiro Omura, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Mitsuru Sato, Yuzo Nagata, Yasuyuki Matsuoka, Yoshihisa Iwata, Hideaki Aochi, Akihiro Nitayama, “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” Symp. VLSI Technology, paper 2-2, pp. 14-15 (2007)
This paper in 2007 introduced a novel 3D NAND flash memory array architecture and method of patterning multiple layers of control gates with a single lithography step. The novel concept limited the number of lithography steps and the layout area used for driver transistors, making 3D NAND Flash commercially viable and enabled the industry to steadily increase 3D NAND storage capacity.