Workshop 4

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The Development of Materials to Systems Co-Optimization (MSCO™) Methodology to Enable Rapid PPCAt Assessment for Advanced Node Technology Development

Organizer : She-Hwa Yen (Applied Materials), El Mehdi Bazizi (Applied Materials)

The industry has entered an era where traditional device scaling is inadequate to deliver node-to-node PPA improvements and, concomitantly, MOL/BEOL parasitics are an increasingly dominant factor for PPA scaling. In this era, advanced node technology development requires a holistic approach that evaluates a combination of levers such as new materials, unit/integrated processes, device architecture, library architecture, circuit architecture as well as system and design implementation. This complex set of interdependent parameters requires a coordinated methodology and platform for rapid iterative analysis to down select the materials, process, circuit topology and architecture choices for optimal system realization. This workshop assembles a panel of experts, across the range of disciplines spanning this methodology, to provide a perspective into advanced node system design and optimization.

About She-Hwa Yen

She-Hwa (Albert) Yen received his Ph.D. from Stanford University in 2011. He is a director of analog design at Applied Materials. Prior to joining Applied he worked at Intel and Industrial Technology Research Institute, Taiwan. His research includes AI/ML, in memory computing hardware design, mixed-signal circuits and high-speed optical transceiver design, broadband circuits for wireline communications.

About El Mehdi Bazizi

El Mehdi Bazizi is Sr. Director of Design Technology and manager of the Modeling group at Applied Materials, Santa Clara, CA. He obtained his Ph.D. in Engineering Physics / Applied Physics, MS in Design of Microelectronic and Microsystems Circuits and BS in Electronic and Digital Technologies in France. Mehdi has extensive Research, Development, and Manufacturing experience (~15 years) at STMicroelectronics, GlobalFoundries, and Applied Materials. He has foundry experience in defining and executing development plans for several technology nodes: planar CMOS (28nm PolySiON/HKMG and 22FDX/12FDX), FinFET 14nm, 7nm, 5nm, 3nm, Gate All Around (GAA), and emerging memory devices (NAND, DRAM, MRAM, ReRAM, Flash). He led modeling teams worldwide, directed multiple R&D projects and advanced technology development. He has authored or co-authored more than 60 papers in international journals/conferences and more than 50 patents. Mehdi has been involved in technical committees for EMRS, SISPAD and ESSDERC, including serving as a Technical Chair of SISPAD 2021.


1. Materials to Systems Co-Optimization: Accelerating Technological Innovations

Never has DTCO been more of a critical requirement than today. Each node brings increased complexity with the growing number of technological innovations, which require a myriad/combination of new process, transistor device, and design knobs. This leads to an explosion of simulative options that need to provide rapid, iterative feedback. The call of the hour is for DTCO on steroids to meet these challenges. In this talk, we present a novel Materials to Systems Co-Optimization™ (MSCO) software platform, expanding the boundaries of traditional DTCO to encompass materials engineering to system design. A case study of MSCO application to enable rapid design prototyping of material and process innovations for AI applications was developed. In this talk, we present an end-to-end case study for analog in memory computing with MSCO to explore and optimize efficiency and performance and numerous trade-offs in materials, design, and neural networks. This accelerates the speed of development and TTM of an efficient analog in memory compute for edge AI applications.

2. Transition from Gate-All-Around to Stacked Transistor Architecture for Logic and SRAM


Currently the industry is transitioning from FinFETs to GAA (Gate-All-Around) technology and will likely have several GAA technology generations in the next few years. What’s next after that? This is the question that we are trying to answer in this project by benchmarking GAA technology with transistors on 2D materials and stacked transistors (CFET). The main objective for logic is to get a meaningful gain in PPAC (Power-Performance-Area-Cost). The main objective for SRAM is to get a noticeable scaling for the SRAM array and its periphery without losing performance and yield. Another objective is to move in the direction that has a promise of a longer term progress, such as start stacking two layers of transistors before moving to a larger number of transistor layers. With that in mind, we explore and discuss the next steps beyond GAA technology.


3. System to Device Co-Optimization for Efficient Development of Analog In-Memory Accelerators

The design of analog accelerators based on emerging memories, such as memristor or ReRAM, requires several interactions between experts of different domains in order to exploit at best the performance of such nanoscale devices. However, the parameters space is often very large, interdependences are not trivial and non-linear analog circuits are complicated to optimize. In this talk, I’ll present AI-based tools that we recently developed at Hewlett Packard Enterprise for analog circuit/memristor tuning and hardware-software co-design able of improving performance above human-experts and exposing interesting trade-offs.

4. Building a Methodology for Design- and System-Technology Co-Optimization

The relative contribution of pure dimensional node-to-node scaling to system performance has diminished. Indeed, much of the value in recent nodes has come from various scaling boosters and materials innovation. The most recent announcements in this area are FinFlex, the switch to backside power delivery and various material innovations such as Molybdenum. Many more are still in the R&D phase, such as Ruthenium for the BEOL or even 2D channel materials. Since the benefits of these scaling boosters are becoming increasingly application dependent, there is a growing need for a solid methodology to assess their value and impact (positive or negative) on the Performance, Power, Area, Cost, Manufacturability, Yield, Reliability, Sustainability, Safety, and Security of supply.

5. Design Technology Co-Optimization Solutions for Enhanced PPAC for CFET Device Architectures

Significant work has been done to quantify the power / performance / area / cost (PPAC) for complimentary FET device architectures as a future extension to gate-all-around technologies now entering into high volume manufacturing. As gate-all-around devices are extending possibly into several technology nodes on the industry roadmap, there is significant push to provide further improvement in power and performance for these CFET devices in order to ensure continuation of node-on-node device scaling. In this presentation we will provide new design technology co-optimization solutions to extend the power and performance of both monolithic and sequential CFET integrations in order to achieve full node improvements over 2nd and even 3rd generation GAA devices, and will evaluate the cost-per-performance of how these solutions are applied between the different integrations of CFET.

6. Application Dependent Architectural Design Technology Innovation and Co-optimization for Feature Rich Technologies

In this paper, we present the Application dependent Design & Technology Co-optimization (DTCO) to develop Differentiated Feature Rich Technologies for customers in the space of edge-AI, ultra-low power, ultra-low leakage (ULP/ULL) and Analog design. 22FDX, a fully depleted transistor (FDSOI) with adaptive body bias (ABB) is a key differentiated technology that offers power performance area-cost (PPAC) advantages for many key applications domains compared to planar technologies. DTCO driven library architecture is presented for ULP/ULL and edge-AI with memory architecture using Synthesizable Logic Memory (SLM). 22FDX enables best node scaling driven by lower supply voltage (VDD/Vmin), reduced leakage or for higher density. Also, Digital and Analog DTCO is applied to improve Standard Cell library and Analog IP to illustrate power of DTCO in driving feature rich technologies driven by application requirements.