Workshop 3

* If you encounter menus do not work upon clicking, delete your browser's cache.

Towards Functional Backside : What’s next after Backside Power Delivery ?

Organizer : Rongmei Chen (imec), Giuliano Sisto (imec), Geert Hellings (imec)

Technology node scaling is driven by the need to increase system performance, but it also leads to a significant power integrity bottleneck, due to the associated back-end-line (BEOL) scaling. Power integrity degradation induced by on-chip Power Delivery Network (PDN) IR drop is a result of increased power density and number of metal layers in the BEOL and their resistivity. Meanwhile, signal routing limits the SoC performance improvements due to increased routing congestion and delays. In this workshop, we will give an overview of the state-of-art of this technology, including the progress and integration that enable this technology, challenges and reliability brought by this technology, and PPA benefits of chips/systems using invite presenters from industries and research institutes that are the main contributors and drivers of this technology.

About Rongmei Chen

Rongmei Chen obtained Bachelor and Ph.D. degrees (with excellent Ph.D. thesis honor) from Tsinghua University, China, in 2012 and 2017 respectively. He was a post-doc at LIRMM-CNRS/Montpellier University, France from 2017 to 2019. He joined imec as a permanent researcher in Leuven, Belgium in 2019. He focuses on 3D IC design and exploration, SRAM macro and SoC design, CNT electronics and IC radiation effect. He has published ~40 papers (19 first-author papers) in journals or conferences including TED, TVLSI, TNS, IEDM, VLSI, NSREC, RADECS, etc. His works have been highlighted by IMEC, European news, and VLSI 2022 conference. He was awarded "Ten Best Progress in China Radiation Physics Field in 2015-2017" for his innovative contribution to the field of radiation effects of IC. He was awarded the European Marie Curie Individual Fellowship in 2019, ranking top 0.7% globally in the Engineering field. He has served as TPC members for several meetings including VLSI-SOC, EDTM etc. and organized a 3D IC workshop in Symposia on VLSI 2021. He got many invitations of technical presentations for the world known semiconducting giants including Intel, Qualcomm, Samsung, TSMC etc. and universities including Stanford University etc.

About Giuliano Sisto

Giuliano Sisto received his B.Sc. and M.Sc. from Politecnico di Bari in 2015 and 2018 respectively. He obtained a Ph.D. from the Universite' Libre de Bruxelles (ULB), in collaboration with imec and Cadence Design Systems, in 2022. Since November 2021 he has been working as a researcher for imec in the Physical Design Research (PDR) group. His research interests include system architectures and their co-optimization with physical design using emerging technologies, pathfinding the next generations of SoC.

About Geert Hellings

Geert Hellings received the B.S. and M.S. degrees in Electrical Engineering from the KU Leuven, Belgium, in 2007. He obtained a Ph.D. degree from the Electrical Engineering Department (ESAT) of the KU Leuven, Belgium and the CMOS Technology Department at imec, Belgium in 2012, working on the integration & TCAD of field effect transistors with high-mobility channel materials for digital logic applications. In 2011, he joined the Device Reliability and Electrical Characterization group in imec, Belgium, researching ESD, LU and I/O. Afterwards he joined the imec DTCO Research as Program Manager (2020) and Program Director (2022). He holds 20+ patents and has authored or co-authored >200 technical papers for publication in journals and presentations at conferences.


1. System and Physical Design

1-1. Backside PDN for Mobile Applications


1-2. Design and Process Considerations for Implementing Holistic Routing : Power Delivery, Clocking, and Signaling


Multiple foundries have announced plans to implement routing on the backside of Si wafers. Initially, these new layers are primarily intended for power delivery. These backside power delivery networks (or BSPDN) offer the potential for significantly reduced IR drop and electromigration tolerance. Additionally moving the power delivery to the backside opens additional routing resources on the front side of the wafer. However, in relocating the PDN to the backside some of the thicker low-impedance layers may be removed from the front side of the die in order to save cost. This may have a negative impact on high-speed signals such as clocks and long-distance point-to-point connections since these signals tend to share the lower-impedance upper routing layers with the PDN. Moving these signals to the backside of the wafer along with the PDN would seem logical. Placing signals on the backside introduces a new process, design, and EDA considerations including choice of material and dielectrics for the backside layers, how to efficiently implement connections between the back and front side of the wafer, design considerations on which signals to allocate to front vs backside, and challenges in the EDA infrastructure to support this new model with signals both below and above the devices. This talk will motivate some of the challenges the process, design, and EDA teams will need to solve to implement a more holistic backside routing system.

1-3. A New VLSI R&D Frontier : Cell-Level Interconnects to Enable Back-Side Power Delivery Networks (BSPDN) and Device Stacking


2. Electronic Design Automation

2-1. Backside Clock Delivery : Opportunities and Challenges from System Design Perspectives


2-2. Enabling Backside Technology Benefits Using Cadence Digital Full Flow

Backside routing is one of the new innovations being deployed as part of the latest advanced node processes. Initially, backside routing was developed for power delivery but is now rapidly expanding to clock and signal interconnect also. Based on the long collaboration with Imec, Cadence will show how backside routing has been integrated into the digital implementation flow, delivering the benefits of this technology.

2-3. Realizing PPA Benefits of Backside Power and Signal Routing Using Synopsys Digital Design Flow


3. Process and Integration

3-1. 3D Integration of SoC Power Delivery : Contacting the Standard Cell Power Grid from the Wafer Backside

The need for increased computing continues growing at an ultra-fast speed, with chip data remarkably still keeping in line with Moore’s law. This momentum is expected to carry on even as 2D scaling becomes increasingly challenging via the introduction of new device architectures and materials, scaling boosters such as BSPDN, 3D chip stacking, and overall DTCO-driven design. Transistor density scaling remains at the core of the roadmap, with continued advances in holistic patterning using EUV/high-NA EUV lithography key for enabling cost-effective scaling and lower energy consumption as it allows a reduced number of process steps/complexity. To take full advantage of multiple innovations at transistor level, de-coupling signal and power wiring by using both wafer sides for routing and moving the latter to the wafer’s backside (BSPDN) is a new concept that has been gaining traction for obtaining higher quality power delivery and enhanced signal integrity. This is a game-changer scaling booster for which various device connectivity configurations are possible, including how the devices are connected and how that gets translated into cell layouts, and it will be the focus of this discussion, highlighting some key integration elements, challenges, opportunities, and early results. Starting from this basic scheme, the concept also has the potential to expand towards other functions namely by addition after BS processing of specific devices (such as I/O and ESD devices, MIM capacitors, ...), or structural interconnects (e.g., for clock distribution, bus, ...), paving the way to a truly functional BS. That fits into a broader vision wherein enhanced system performance is expected to be obtained by leveraging the unique capabilities of logic, memory and 3D technologies under the umbrella of STCO into a future CMOS heterogeneous platform: CMOS 2.0.

3-2. Evolution of Backside PDN and its Impact on Lithography

Backside-PDN is an innovative approach to increase transistor density against the backdrop of a slowdown in pitch scaling. Aside from a straightforward transistor density increase due to a decrease in cell area and a relative increase in routing resources, it also opens up a whole set of new opportunities, such as the separate optimization of the frontside BEOL for signal routing, and the backside BEOL for power distribution in terms of materials and geometry, enabling all kinds of new choices. As these structures on the backside need to connect to the structures on the frontside, a tight overlay between the frontside and the backside is required. Achieving the desired overlay is made harder by distortions in the bonded wafer resulting from bonding the chip wafer to a carrier wafer and subsequent thinning of the bonded wafer. I will be discussing a number of ways to create a backside-PDN and the resulting requirements in backside-frontside overlay, which need to be accomplished by (i) a reduction in the distortions introduced in the (bonding/thinning) process and (ii) corrections applied during the lithographic patterning of the backside.