Workshop 2

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EUV Lithography & Path to High NA EUV Patterning Solutions

Organizer: Allen Gabor (IBM)

EUV lithography has been used in high-volume production since 2019 and by 2025 high NA EUV is expected to be implemented. To achieve the theoretical resolution capability of EUV, and especially high NA EUV, both the high NA EUV tool and all the supporting infrastructure need to be developed. New resist materials and improved EUV masks are two key supporting infrastructure areas. The development of the high NA tool and its implications to chip design and layout are also critical for the semiconductor community to understand. This workshop will cover many aspects EUV and the transition to high NA EUV including.

About Allen Gabor

Allen Gabor is a Senior Technical Staff Member at IBM. He has worked in the field of lithography at Arch Chemicals, GlobalFoundries and IBM. This work has included photoresist development, CD control, overlay minimization and 193 dry, immersion and EUV insertion. He received his PhD (1996) in Materials Science and Engineering from Cornell University based on his work on block copolymer photoresists. He is the author of more than 50 journal papers and holder of over 30 patents. He currently serves on the program committee for SPIE Extreme Ultraviolet (EUV) Lithography Conference and is a senior member of SPIE.

1. Development of Current EUV Tools and Future High NA Tools

Development of current EUV tools and future high NA tools: Overview of development that has enabled current 0.33 NA EUV lithography and work needed to enable the high NA EUV lithography to be successfully implemented.

2. Novel Resists to Achieve Promised High NA EUV Resolution

Novel resists: Novel dry resists have demonstrated industry leading resolution and defectivity. Work is in progress to enable dry resist solutions concurrent with the introduction of high NA EUV. Demonstration of the path to implementation and progress of the materials to enable the full entitlement of the resolution capability of EUV lithography will be presented.

3. EUV and High NA EUV Mask Challenges

EUV and high NA EUV mask challenges: There are numerous issues that become much more difficult with high NA EUV for masks. This includes CD and image placement control where multibeam mask writers, advanced resist processes and improved stitching accuracy management are key. Increased focus on development of new absorbers and on appropriate pattern transfer processes to decrease mask 3D effects is also required.

4. High NA EUV Exposure Tool Implications to Chip and Mask Layouts

High NA EUV exposure tool implications: The anamorphic nature of the high NA EUV (4x magnification in X and 8x magnification in Y) results in a field size exactly half that on current EUV and optical tools. When using high NA tools in a semiconductor build that will also use full field tools, there are overlay implications and chip and mask layout issues that need to be optimized.

5. Resolution Capability and Stitching of Features Across the High NA Exposure Fields

High NA EUV imaging: The resolution for High NA EUV goes down to 20nm pitch and below, enabled by the 0.55NA projection optics featuring a central obscuration. It will be shown how the best imaging performance on wafer can be achieved by doing a careful optimization of the illumination source and mask (stack), balancing image contrast, depth of focus and exposure dose. In addition will be presented how stitching of half fields can be enabled by mask black border and absorber reflectivity control, as well as aerial image crosstalk and double flare maps being included in the OPC flow.