Workshop 9
Hybrid Bonding – Breaking Boundaries in Advanced Packaging and Heterogeneous Integration in the Era of Chiplets and AI
Organizer : Haris Khan Niazi (Intel Corporation)
Organizer : Mehdi Saligane (University of Michigan)
Organizer : Georgios Dogiamis (Intel Corporation)
As the semiconductor industry moves into a new era for AI and high-performancecomputing, advanced 3D packaging of chiplets employing Hybrid Bonding technologyis becoming essential to continue Moore's law in the next decade. This technology allows for high performance by integrating seamlessly components like logic, memory, and optics into compact, scalable, multi-functional systems. However, it also brings challenges in intelligent context-aware process control, metrology, and inspection to ensure yield, quality and reliability.
This workshop will explore the latest advancements in process optimization integrating the best-in-class and cost affordable equipment and novel materials that are required to address the technical challenges for the sub-micron interconnect scaling and the new metrology solutions needed for these innovations such as ultra-dense sampling highthroughput surface topography, real-time defect analyses, subsurface void detection, material characterization, and more. Via expert-led discussions, participants will gain the knowledge to tackle these challenges and improve 3D packaging integration. Whether you're a technologist, researcher, or engineer, join us to stay ahead in this transformative era of packaging innovation!"
About Haris Khan Niazi
Haris Khan Niazi is an Advanced Packaging R&D Engineer in the Technology Research division at Intel Corporation. Haris leads hybrid bonding and 3D HI metrology and inspection with expertise in strategic roadmap definition and developing scalable solutions for sub-micron pitch interconnect technology. His research interests and contributions are focused on high speed, high resolution surface topography characterization, novel defect detection techniques and metrology induced design co-optimization. He actively contributes to conferences like ECTC and IEDM, and holds several patents in the domain of hybrid bonding overlay and innovative packaging solutions. Haris holds a Masters' degree in Photonics and Optical Sciences from the University of Arizona, and a Bachelors' degree in Electrical Engineering from LUMS, Pakistan.
- 1. Hybrid Bonding Outlook for Chip-to-Wafer Memory Stacking, Kunal Parekh, Micron Inc.
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Abstract:
As High Performance Computing is driving advances in interconnects enabled by packaging of chiplets, 2.5D and 3D integration are required to enable the complex package solutions. Memory is leading this with 3D integrated products like HBM which are then part of a 2.5D solution. Micron and our partners in the industry are leading the development of architectures, memory systems and process technology to enable this revolution. We will explore the challenges in Processing, Measuring and Testing these complex heterogeneously integrated Si systems - 2. Metrology and Inspection Challenges in Hybrid Bonding for Advanced Packaging and Heterogeneous Integration, Yusin Yang, Samsung Electronics Co.
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Abstract:
Hybrid bonding is transforming advanced packaging and heterogeneous integration, particularly in the era of chiplets and AI. This technology enables high-density interconnects with superior electrical performance and power efficiency but also introduces critical challenges for metrology and inspection.
This work focuses on metrology’s role in tackling these challenges, such as ensuring precise alignment, large area 3-dimensional topology and warpage metrology at both wafer level and chip level. In terms of inspection, as the packaging generation evolves, the stacking layer increases, strengthening the need for nanoscale defects and void detection at the lower interface.
Advanced techniques, including optical inspection, X-ray microscopy, atomic force microscopy, and acoustic microscopy are examined alongside AI-powered solutions for defect classification and integrated analysis of step-by-step inspection and metrology data.
By addressing these challenges, metrology and inspection play a pivotal role in advancing hybrid bonding, enabling the next generation of high-performance, AI-optimized semiconductor devices. - 3. Unlocking the next generation of Hybrid Bonding, Jonathan Abdilla, Besi
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Abstract:
The emergence of heterogeneous integration and the era of chiplets, accelerated by the adoption of Universal Chiplet Interconnect Express (UCIE) has significantly increased the demand for higher connection density and bandwidth, lower latency and modular die sizes in a single package. Die-to-wafer (D2W) hybrid bonding has become a key contender in addressing this demand by directly bonding logic/memory die onto a target wafer. However this technology presents new challenges in precision placement and interface material interaction. This talk will demystify D2W bonding from the perspective of a high throughput, high accuracy bonder as well as real world findings and key performance factors. - 4. Wafer bonding challenges and the resolution of paths, Ilseok Son, TEL
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Abstract:
Wafer bonding is one of key modules in 3D Integration & Heterogeneous Integration proving for a next generation scaling resolution path. In this talk, wafer bonding type, process flow, and challenges in 3DI bonding and 3DI metrology will be introduced. In addition, TEL’s research work on the challenges will be discussed. This discussion covers wide range of topics including incoming wafer condition’s impact on bonding void & alignment, plasma surface activation modeling & yield impact, bonding alignment impact on e-test with 0.5um pitch hybrid bonding, Cu recess/ oxidation characterization & resolution, improved bonding energy measurement method, and wafer distortion modeling. - 5. JDevelopment of Polymer Hybrid Bonding toward to 3D packaging integration, Takenori (Ken) Fujiwara, Toray Industries Inc.
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Abstract:
Chip-to-wafer (C2W) hybrid bonding technology is being developed to implement multiple semiconductor chips to the substrate for heterogeneous integration packages. We are focusing on polymer hybrid bonding due to advantage from 1) dust insensitive, 2) low-temp process flow 3) enough adhesion of bonding interface and 4) low chip warpage. We will report that the results of concept from 1) to 4), demonstration of muti-chip tacking and daisy chain electrical test." - 6. Unique Challenges of D2W Hybrid Bonding for Logic and Memory Applications, Jinho An, Applied Materials Inc.
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Abstract:
Heterogenous integration and advanced packaging is behind the technology that is enabling today’s AI and high-performance computing. This is done through complex architecture that utilizes platforms including microbumps, through silicon vias (TSV), high density fanout and hybrid bonding (HB). The integration of chiplets using any combination of these technologies is allowing the industry to extend the Moore’s law and overcome limitations of the Von Neumann architecture. Hybrid bonding is an especially appealing technology that helps improve power and performance (higher I/O density), as well as thermal management. Sub-10 ㎛pitch die-to-wafer (D2W) HB is already in production1) for logic applications, and the industry is working to implement HB technology for memory applications as well. However, there are challenges for D2W that require new innovation in both processing and metrology & inspection (M&I), and also unique challenges for both logic and memory applications specific to its integration. The presentation will focus on how logic and memory HB technologies are different and what process and M&I technologies are needed to facilitate HVM of the HB technology across different applications. Process challenges including low temperature bonding, die warpage management and dicing will be discussed, while M&I challenges will include topics on particle inspection and surface metrology.
1) R. Agarwal et al., “3D Packaging for Heterogeneous Integration” IEEE Electronic Components and Technology Conference (ECTC), July 2022. - 7. Enabling In-Line Process Control for Hybrid Bonding Applications in HPC and AI, Monita Pau, Onto Innovation
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Abstract:
Hybrid bonding has long been used in the manufacturing of CMOS image sensor devices and 3D SoC products using this technology have also been released in recent years. Direct Cu-Cu bonding is poised to succeed microbumps in devices requiring high-bandwidth data transfer. As known good dies/wafers are being bonded together, stringent process control is required every step along the way to ensure the final stacked product is of high yield. Bonding surface topography monitoring and the detection of particles, cracks and voids are some of the critical process control parameters in hybrid bonding. In this presentation, we will discuss the various metrology solutions addressing these needs - 8. High-Throughput In-line AFM Metrology for Hybrid Bonding applications, Hamed Sadeghian, Near Field Instruments
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Abstract:
Maintaining high yield in hybrid bonding—whether wafer-to-wafer or chip-to-wafer—depends on preventing voids at the bonding interfaces. This requires strict control over the surface roughness of both copper (Cu) and dielectric materials, as well as precise control of Cu pad dimensions in the x, y, and particularly z axes. Atomic Force Microscopy (AFM) is the primary non-destructive technique employed in hybrid bonding to measure Cu-to-Cu and dielectric-to-dielectric bonding, dishing, erosion, and wafer edge roll-off. However, the limited throughput of conventional AFM systems has constrained its adoption in high-volume manufacturing, where minimizing wafer queue times is as critical as ensuring accurate data collection for large-scale statistical analysis.
In this work, we demonstrate the use of high-throughput AFM, capable of capturing several megapixels per second, for metrology of hybrid bonding copper pads and the surrounding dielectric. Key performance metrics, including precision and throughput, are reported. Additionally, we present results from long-range (tens of millimeters), low-frequency topography measurements of the dielectric, with a focus on transition regions between active bonding pads and adjacent density variations. - 9. Innovative metrology solutions for HB process challenges in Advanced Packaging, Andrew Lee, Nova
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Abstract:
Recent advances in semiconductor devices, driven by data centers, HPC, and AI, focus on performance, efficiency, and scalability. Central to these improvements is 3D integration within advanced packaging, with Hybrid Bonding (HB) emerging as a critical technology. However, HB introduces process challenges such as dielectric surface topology, defect control, Cu recess, wafer alignment, warpage, interface voids, and bond strength.
In process control, wafer areas are divided into inner and outer fields. The inner field requires precise control of surface topology and roughness, while the outer field addresses edge roll-off (ERO) and bevel defectivity. Managing ERO involves wafer thinning, surface uniformity improvements, and advanced planarization techniques. Additionally, Copper dishing, an uneven erosion during the CMP process, must be closely monitored to ensure surface planarity and reliable interconnect bonding.
This session explores advanced pre-bonding HB metrology solutions, utilizing optical scatterometry and spectral interferometry combined with OCD modeling. These approaches enhance precision in managing ERO and Cu recess, ensuring robust bond strength, electrical performance, and mechanical integrity. By addressing these challenges, the hybrid bonding process achieves higher yields and reliability, supporting next-generation semiconductor innovation. - 10. Inspection, Metrology, and Process Challenges in Die-to-wafer Hybrid Bonding, Chet Lennox, KLA
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Abstract:
The use of die-to-wafer hybrid bonding technology holds significant promise towards more tightly integrated logic and memory components in high-performance and low-energy computing. But with that promise comes significant challenges as compared to conventional solder-based die stacking techniques. Surface cleanliness of both particulate and organic contamination must be more stringently controlled, driving inspection sensitivity requirements higher and the adoption of new processes like plasma dicing for singulation. Pre-bonding surface dielectric and copper profiles must be carefully tuned to create a successful interface, necessitating high precision and throughput metrology of nanometer scale features. In addition, both macroscopic die and wafer shape become important to control, as they both contribute to bonding strength and alignment accuracy. With bonding x/y alignment being such an important parameter for the pick-and-place tools, post-bonding overlay metrology with innovative and flexible fiduciary techniques must be used. Lastly, post die-placement dielectric gap fill has become a key enabler for downstream process enablement. In this talk, KLA will briefly review our experience with these challenges to enable high-quality and economical hybrid bonding for the industry.