Workshop 8
Manufacturing Advanced VLSI Systems using Virtualization and Machine Learning
Organizer : Joseph Ervin (Lam Research) Machine learning (ML) and virtualization have become powerful tools that support both semiconductor research and development (R&D) and high-volume manufacturing (HVM). Machine learning provides an effective solution to the “large data” challenges present in many semiconductor manufacturing applications. Virtual twins provide real-time analogs of semiconductor tools and devices and can be used to minimize the time and cost of physical experimentation and wafer-based development. Chipmakers, equipment manufacturers and software companies are developing and deploying virtualization and machine learning technologies throughout semiconductor manufacturing in a wide range of applications, including next node design, process optimization, metrology, lithography, equipment control and many other critical areas.In this workshop, we will discuss best practices in the design and deployment of virtual twins and AI/ML solutions for semiconductor manufacturing. Executives and industry thought leaders in chip manufacturing, process development, metrology, lithography and other critical semiconductor manufacturing applications will review real-life examples of using virtualization and machine learning technologies to accelerate advanced semiconductor manufacturing.
Dr. Joseph Ervin is the product line head of Semiverse? Solutions group at Lam Research. Dr. Ervin joined Lam Research in 2017 as a part of Lam’s acquisition of Coventor. Previously, he worked for IBM on semiconductor device and integration development at multiple research and foundry locations, including IBM, ST Microelectronics, the College of Nanoscale Science and Engineering, and at GlobalFoundries. His current position includes managing software product development and deployment for next node semiconductor integration challenges, along with development of unique methods for modeling and solving these issues. He holds a Ph.D. in Device Physics from Arizona State University. He has over 60 issued patents and over 50 publications.
Technology, and semiconductor technology in particular, has been advancing at a rapid and accelerating pace since the invention of the transistor over 75 years ago. We’ve now reached the point that “virtual” silicon twins and artificial intelligence are helping to produce the next generation of computer chips. This has a created a virtuous cycle of innovation, where computer chips and machine learning are helping to produce new, more powerful VLSI devices, but even faster and better than before. Virtual silicon models, that include virtual fab processes and virtual metrology data, are now an integral part of the digital transformation of semiconductor manufacturing.
The combination of virtual twins and ML/AI enables real-time monitoring and adaptive control of complex manufacturing environments. They help reduce downtime, enhance scalability, and improve resource efficiency, contributing to sustainable production practices. In this workshop, I am going to explore the transformative potential of virtual twins in manufacturing Advanced VLSI Systems to enhance semiconductor yield, reduce defect density, and streamline manufacturability. By creating high-fidelity digital replicas of fabrication processes, virtual twins enable precise simulation and analysis, allowing engineers to identify process bottlenecks, predict defects, and optimize materials and equipment setups before physical production. We will examine how these virtual models can bridge the gap between design and fabrication, improving collaboration between foundries and IDMs, equipment manufacturers, material suppliers, EDA tool providers, and research consortiums. Attendees will gain insights into how Dassault Systèmes, in partnership with leading semiconductor companies, universities, and government institutions, is exploring the use of ML/AI to address the challenges of model accuracy, data integration, scalability, interdisciplinary collaboration, validation and calibration.
The opportunities for value creation by applying machine learning (ML) techniques in semiconductor manufacturing is enormous, ranging from aiding design engineers, process and integration engineers to fab operators, and for improving processes and yield. The complexity, though, of using different sensitive data sources and creating federated AI solutions in the ecosystem is big as well. In the past, Imec researchers have addressed Privacy-Preserving Amalgamated Machine Learning (PAML) techniques to enable model creation between privacy silos, without leaking sensitive information. Due to the evolution towards data-efficient hybrid modelling techniques, combining ML with physics-based models, or even replacing the traditional simulations with physics-informed ML, the number of features that need to be securely exchanged increases. So does the complexity, when including continuous learning capabilities with new data. If we want to scale to the level of digital twins of process modules and/or integration flows, we will need hierarchically distributed digital twins, across different tools and companies while protecting sensitive insights. Imec will provide future Digital Twin insights, including new patterns for attesting trust & security levels in a scalable ecosystem of semiconductor partners.
Advanced technology nodes introduce new challenges for maximizing power and performance while maintain high yield. Provisional process technology ground rules change over time. It is important to assess the impact of variability to standard cell performance to understand the underlying ranking of ground rules as well as highlight areas for improvement. SiClarity will present predictive process window results on a GAA 4 track process flow with backside power showing the impact of variability to performance as well as examining trade-offs in process variability tolerant designs to overall performance. Via and metal line EPE will be examined as well as variations in epi contact and tip to tip performance. The range of variability will cover current capability as well as future tool and process roadmap specs.Four standard cells will be examined including MUX, AOI, INV and a latch. Performance assessments will use a combination of rigorous and predictive layout parasitics as well as a range of GAA compact device models. Results will highlight process center in terms of F max for a fixed power as well as the impact of variability and the pareto of variability factors most impacting performance.
During semiconductor manufacturing, Statistical Process Control (SPC) ensures that products will meet final Electrical Wafer Sort (EWS) tests. Due to the expense in cost and throughput associated with measuring every wafer in every lot for every product, the SPC measurements are sparse and often insufficient to create accurate and predictive models of EWS targets. In this workshop, we present examples of real-life applications of process virtualization from Front-End-Of-Line (FEOL) to Back-End-Of-Line (BEOL) processes, along with strategies to overcome lack of relevant data via feature engineering. In addition, we will explain the benefits of dedicating targeted sampling and sensors alongside the most impactful processes along a full production line and how, in many instances, full process optimization can only be achieved when the interactions between multiple processes are accounted for.
The goal of this seminar is to provide participants with an overview of how virtualization and machine learning are impacting the development and manufacturing of advanced VLSI systems.
About Organizer
In this talk, we will discuss how semiconductor production is being aided by virtual silicon and “virtual twins”, and will discuss innovative techniques that use virtual silicon to address high volume semiconductor manufacturing challenges. These techniques include virtual process modeling, virtual metrology, and virtual process optimization with design of experiments (DOEs). Machine learning is also valuable in virtual silicon modeling, and can complement human intelligence and experience to improve manufacturing and yield. Specific examples of using these tools to provide real-time feed-forward and feedback optimization will be discussed during this session, with demonstrated improvements highlighted in semiconductor manufacturability and yield.