Workshop 7
What is Possible with Open Chip Design? The Journey so Far.
Organizer :Mehdi Saligane (Brown University) Building on the success of the 2023 workshop, "Open Source PDKs and EDAs: Community Experiences Toward Democratization of Chip Design," which drew nearly 180 attendees, this year’s session delves deeper into the transformative role of open-source methodologies in VLSI design. The previous workshop highlighted key milestones, such as the Open MPW shuttle program’s facilitation of over 500 project submissions, alongside diverse insights from academia, industry, and government.
Mehdi Saligane is an Assistant Professor at Brown University. He is also a visiting faculty at Google Research. He was previously a Research Faculty member and lecturer at the University of Michigan. His research interests include low-power and energy-efficient IC design, Bio Sensors, Open-Source EDA, and analog and mixed-signal IC design automation. He is the recipient of the Google Cloud Research Innovators Award and the Google Research Faculty Award in 2023 and 2021, respectively. Dr. Saligane currently chairs the Technical Committee of SSCS’s open-source ecosystem (TC-OSE). He is also the co-founder and organizer of the SSCS Code-a-Chip Notebook Competition at ISSCC and VLSI Symposium and the SSCS Chipathon Design Contest.
Deploying machine learning in EDA has proven to be very challenging due to EDA tool license costs, Execution machine costs, EDA tool restrictions on benchmarking, along with access to proprietary PDK and proprietary design data.
The speaker has been leading the MakeLSI Project for ten years. This project aims to realize a world where everyone can design and fabricate LSI. One of its key factors is open source in design tools, design kits, and fabrication. The speaker will present the knowledge and experiences from past activities of this project, as well as its current status. The speaker will also discuss LSI fabrication methods, the last missing piece for open-source silicon
Veryl, a hardware description language based on SystemVerilog, offers optimized syntax tailored for logic design, ensuring synthesizability and simplifying common constructs. It prioritizes interoperability with SystemVerilog, allowing for smooth integration with existing projects while maintaining high readability. Additionally, Veryl includes a comprehensive set of development support tools, such as package managers and real-time checkers, to boost productivity and streamline the design process. These features empower designers to conduct high-quality hardware design efficiently. Veryl compiler and all related tools are provided as open-source software, and discussion about language specifications and tool features is published on GitHub. In this presentation, we talk about Veryl’s features and development.
This presentation outlines a systematic procedure for analog circuit sizing using open-source tools, invoking the well-known approach using precomputed look-up tables and gm/ID as a proxy for the transistor’s inversion level. The overall flow is Python-based and begins with a baselining phase where an existing circuit is used to “calibrate” the design equations for subsequent specification-driven sizing. A simple 5-transistor OTA is used to illustrate the methodology using Ngspice and SkyWater’s 130 nm open-source PDK.
For several years, our group maintains a collection of open-source IC EDA tools, called the IIC-OSIC-TOOLS (https://github.com/iic-jku/IIC-OSIC-TOOLS). This set of tools is distributed pre-integrated as a virtual machine image, and allows analog, mixed-signal, and digital design with the currently available open-source PDKs. We are using this tool collection in our curriculum, where we teach bachelor and master-level courses using these tools, including tapeout classes using the Tiny Tapeout framework.|We are further developing an open-source analog circuit design course (https://iic-jku.github.io/analog-circuit-design), where we follow a hands-on approach using the above tools and combine circuit analysis (using modern methods like gm/Id sizing in Jupyter notebooks) with circuit entry and simulation for a holistic experience.
Open-source hardware is on the footpaths of its much successful sibling, open-source software, with a delay of roughly 25 years marking these days the time that we believe will shape its future significantly. Unlike software, open-source hardware will continue to rely on a costly and complex manufacturing flow and its success requires contributions in equal parts from open source-designs, design automation tools and manufacturer information (PDKs) which made open-source developments in hardware more challenging. It may have taken a bit of time, but currently the open-source eco-system is much more mature than many realize and offers significant benefits that go far beyond reducing licensing costs.|For the last 12 years, our group at ETH Z?rich and the University of Bologna has been very active in open-source hardware, and recently, we have shown that significant designs can already be designed and manufactured using an end-to-end open-source design flow. Based on our experience we will highlight the opportunities that open source IC Design brings for teaching, research and commercial exploitation and discuss the challenges that still remain ahead of us.
The advent of Large Language Models (LLMs) powered by Transformer architectures has ushered in a new era of artificial intelligence. However, the substantial computational and memory demands of these models have largely confined them to the cloud, creating a bottleneck for real-time, interactive, and privacy-sensitive applications. A multidisciplinary co-design approach is crucial for co-optimizing models and hardware, enabling custom-silicon LLM architectures on edge devices ? automation of which is enabled by open source frameworks such as OpenROAD and OpenFASOC. We delve into the challenges posed by the "hardware lottery" and "model architecture lottery," presenting strategies to overcome these limitations and optimize for power, performance, area (PPA), as well as model capability utilizing these open source frameworks. We showcase concrete examples of this co-design approach, including a fully parallelized Softmax, illustrating how both questioning core algorithms and embracing a multidisciplinary mindset can find new solutions. Finally, we present open-source automation frameworks built around the open-source tooling designed to streamline and accelerate the co-design process itself, highlighting Open-Source’s potential to democratize the design of specialized AI hardware, in the spirit of programs like OpenMPW. Through advancing open-source tooling for multidisciplinary, hardware-software-model co-design, we believe it will be possible to unlock the full intelligence of LLMs at the edge, paving the way for an "AI of Things" characterized by seamlessly integrated, locally intelligent machines and usher in an era of unprecedented possibilities for real-time interaction with locally-intelligent machines.
AI is accelerating into the generative era and it is poised to disrupt multiple businesses, especially as AI capabilities are being "embodied" everywhere, from earbuds to cars. Embodied AI needs to tackle major challenges in energy efficiency, safety, security, and real-time predictability while curtailing computational complexity. In this talk I will focus on chip and system design for embodied AI, moving from ultra-low power AI-accelerated MCUs for smart wearables to large Chiplet-based systems-in-package for intelligent cars and satellites. I will emphasize the strategic importance of an end-to-end (models, software, instruction set architecture, digital IPs, EDA, PDKs) open-platform approach to ensure a healthy innovation ecosystem, long term sustainability, safety and security.
In this presentation we will discuss the latest progress and future directions in the development of the IHP open Process Design Kit (PDK). We will provide an overview of upcoming projects and a roadmap for new features such as PDK support for open source radiation hard and RF designs. We will also present initial results from open source designs developed based on the free design space in IHP open source MPW runs. A cost reduction concept for future open source ASIC designs will also be presented. Finally, open source EDA activities in which IHP is involved on a European level will be addressed.
This year, the focus shifts to the broader impact of open-source PDKs, EDA tools, and collaborative platforms in shaping innovation within the global chip design community. The program features prominent speakers who will share their latest experiences and discoveries, including the integration of open-source workflows into education and industry, the unique challenges and opportunities of open silicon prototyping, and the novel applications emerging from democratized design ecosystems.
About Organizer
Open-source EDA tools with innovative estimation capabilities coupled with open PDKs and designs can overcome these bottlenecks. Proprietary EDA tool companies earn revenue from license cost and have no incentive to create fast estimation tools to alleviate the high machine and license cost to perform training and learning experiments. Open-source tools are driven by users intentions and are very motivated to solve these problems.
The talk will focus on OpenROAD and how this open-source EDA solution can be used to unlock the power of machine learning in a cost-effective way for designers. This unlocking can take multiple forms. For example, using ML to determine which of N RTL implementations is better from a final implementation perspective would help create a more physically aware RTL. Using ML to train machines to make important physical design decisions for floorplanning and other key physical design decisions could also improve productivity. The talk will discuss these issues and how to unlock them in the EDA and design ecosystem.
In this workshop contribution, we will detail our contributions outlined above, and talk about our experience in VLSI teaching and research using open-source tools.