Symposium on VLSI Technology and Circuits

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What is Possible with Open Chip Design? The Journey so Far.

Organizer :Mehdi Saligane (Brown University)
Organizer : Makoto Ikeda (University of Tokyo)

Building on the success of the 2023 workshop, "Open Source PDKs and EDAs: Community Experiences Toward Democratization of Chip Design," which drew nearly 180 attendees, this year’s session delves deeper into the transformative role of open-source methodologies in VLSI design. The previous workshop highlighted key milestones, such as the Open MPW shuttle program’s facilitation of over 500 project submissions, alongside diverse insights from academia, industry, and government.

This year, the focus shifts to the broader impact of open-source PDKs, EDA tools, and collaborative platforms in shaping innovation within the global chip design community. The program features prominent speakers who will share their latest experiences and discoveries, including the integration of open-source workflows into education and industry, the unique challenges and opportunities of open silicon prototyping, and the novel applications emerging from democratized design ecosystems.

About Organizer

Mehdi Saligane is an Assistant Professor at Brown University. He is also a visiting faculty at Google Research. He was previously a Research Faculty member and lecturer at the University of Michigan. His research interests include low-power and energy-efficient IC design, Bio Sensors, Open-Source EDA, and analog and mixed-signal IC design automation. He is the recipient of the Google Cloud Research Innovators Award and the Google Research Faculty Award in 2023 and 2021, respectively. Dr. Saligane currently chairs the Technical Committee of SSCS’s open-source ecosystem (TC-OSE). He is also the co-founder and organizer of the SSCS Code-a-Chip Notebook Competition at ISSCC and VLSI Symposium and the SSCS Chipathon Design Contest.

Introduction
1. Toward a world where everyone can design and fabricate LSI, Junichi Akita, Kanazawa University: Abstract

Dr. Akita has been leading the MakeLSI project for ten years, with the goal of creating a world where everyone can design and fabricate LSI (Large-Scale Integration) chips. A key factor in this initiative is the use of open-source elements in design tools, design kits, and fabrication processes. This presentation will share insights and experiences from the project's past activities, as well as its current status. Furthermore, it will cover LSI fabrication methods, which are essential for achieving open-source silicon.

Bio

Junichi Akita received BS, MS, and Ph.D from University of Tokyo in 1993, 1995, and 1998, respectively. He worked for Kanazawa University from 1998, and then for Future University Hakodate from 2000, and for Kanazawa University from 2004 until now. His research interests are in CMOS image sensor design, LSI design and application for hardware innovators.
2. Open PDK initiative & free open source MPW access in IHP technology, Frank Vater, IHP (TBC): Abstract
The "Open PDK initiative & free open source MPW access in IHP technology" explores the motivation, development, and practical realization of a free open-source PDK for IHP’s G2 BiCMOS technology. The talk begins with the motivation behind the initiative: enabling academic, hobbyist, and startup communities to access professional BiCMOS processes without prohibitive costs or restrictive licensing. A brief historical overview outlines the development of the open source PDK and its integration into widely used toolchains.

The implementation phase encountered several technical challenges, including the translation of PDK data for proprietary design platforms into open standards, validation of process design rules, and ensuring compatibility with existing open source EDA tools. The initiative has been supported by public funding, which played a crucial role in covering development and MPW manufacturing costs.

Finally, the talk provides practical details on how and when users can access the free MPW shuttles, including eligibility criteria, application procedures, and timelines.

Bio

Frank Vater studied information and media technology at Technical University of Cottbus (Germany) and recieved his master degree in 2007. He joined as scientist in IHP with main focus on hardware development for microcontroller and cryptographic cores. In 2017 he got his PhD in area of secure scan-chain test of ASICs. Finally he joined the position of project leader for PDK development in IHP in 2018.
3. Gm/ID-Based Analog Circuit Sizing Using Open-Source Tools, Boris Murmann, University of Hawaii: Abstract
This presentation outlines a systematic procedure for analog circuit sizing using open-source tools, invoking the well-known approach using precomputed look-up tables and gm/ID as a proxy for the transistor’s inversion level. The overall flow is Python-based and begins with a baselining phase where an existing circuit is used to “calibrate” the design equations for subsequent specification-driven sizing. A buffer circuit using a 5-transistor OTA is used to illustrate the methodology.

Bio

Boris Murmann is a Professor of Electrical and Computer Engineering at the University of Hawaiʻi at Mānoa. From 2004-2023 he served as a Professor of Electrical Engineering at Stanford University. His research interests are in mixed-signal integrated circuit design, including sensor interfaces, A/D and D/A conversion, high-speed communication, embedded machine learning (tinyML) as well as open-source chip design. He is a fellow of the IEEE and the incoming Editor-in-Chief of the IEEE Journal of Solid-State Circuits.

4. End-to-end open-source IC design, Frank K. Gürkaynak, ETH Zürich: Abstract
Open-source hardware is on the footpaths of its much successful sibling, open-source software, with a delay of roughly 25 years marking these days the time that we believe will shape its future significantly. Unlike software, open-source hardware will continue to rely on a costly and complex manufacturing flow and its success requires contributions in equal parts from open source-designs, design automation tools and manufacturer information (PDKs) which made open-source developments in hardware more challenging. It may have taken a bit of time, but currently the open-source eco-system is much more mature than many realize and offers significant benefits that go far beyond reducing licensing costs.

For the least 12 years our group at ETH Zürich and University of Bologna has been very active in open-source hardware and recently we have shown that significant designs can already be designed and manufactured using an end-to-end open-source design flow. Based on our experience we will highlight the opportunities that open source IC Design brings for teaching, research and commercial exploitation and discuss the challenges that still remain ahead of us.

Bio

Frank has obtained his B.Sc. and M.Sc. degree from Istanbul Technical University and his Ph.D. from ETH Zürich. He currently is a senior scientist working on computer architectures in the group of Luca Benini and director of the Microelectronics Design Center at ETH Zürich. He has been involved in the Parallel Ultra Low Power (PULP) platform project since its start in 2013 and has been a vocal advocate for open source activities.
5. Open-Source Analog Circuit Design Course With IC Emphasis, Harald Pretl, Johannes Kepler University, Linz, Austria: Abstract
The advent of open-source IC design tools together with open-source manufacturable process development kits (PDKs) allows the creation and distribution of interactive teaching materials in an open way. Utilizing a compiled EDA tool collection (the IIC-OSIC-TOOLS), complete for practical analog and digital IC design, an analog circuit design course for integrated circuits is presented where every component is open source and geared for collaboration: Course notes including source code, Jupyter Notebook-based sizing scripts using the gm/Id methodology, as well as practical circuit examples and simulation test-benches.

Bio

Harald Pretl received a Dipl.-Ing. degree from Graz University of Technology and the Dr. techn. degree from the Johannes Kepler University. From 2000 to 2022, Harald held various industry positions with Infineon, Intel, and Apple. Since 2015, he has been a full professor, heading the Department for Integrated Circuits at JKU, and maintaining the IIC-OSIC-TOOLS.
6. Toward End-to-End Open Platforms and Chips for Embodied AI, Carlo Reita, Fondazione Chips-IT: Abstract
AI is accelerating into the generative era and it is poised to disrupt multiple businesses, especially as AI capabilities are being "embodied" everywhere, from earbuds to cars. Embodied AI needs to tackle major challenges in energy efficiency, safety, security, and real-time predictability, while curtailing computational complexity. In this talk I will focus on chip and system design for embodied AI, moving from ultra-low power AI-accelerated MCUs for smart wearables to large Chiplet-based systems-in-package for intelligent cars and satellites. I will emphasize the strategic importance of an end-to-end (models, software, instruction set architecture, digital IPs, EDA, PDKs) open-platform approach to ensure a healthy innovation ecosystem, long term sustainability, safety and security.

Bio

Carlo Reita received his Laurea di Dottore in Fisica from Roma University “La Sapienza.” From 1988 to 2024, he held various positions at GEC-Marconi, Thomson-CSF, Photronics, and CEA. Since August 2024, he has been CEO of the new Italian RTO for circuit design, Fondazione Chips-IT.
7. Veryl: A New Hardware Description Language Developed as Open-Source Software, Naoya Hatta, PEZY Computing, K.K.: Abstract
Veryl, a hardware description language being developed as open-source software, offers optimized syntax tailored for logic design, ensuring synthesizability and simplifying common constructs. It prioritizes interoperability with SystemVerilog, allowing for smooth integration with existing projects while maintaining high readability. Additionally, Veryl includes a comprehensive set of development support tools, such as package managers and real-time checkers, to boost productivity and streamline the design process. These features empower designers to conduct high-quality hardware design efficiently.

Bio

Naoya Hatta is a senior processor engineer at PEZY Computing, K.K. He has experience designing ASICs for digital signal processing and MIMD many core processors for accelerators. He also contributes to OSS, creating Rust libraries and SystemVerilog utilities.
8. Using Open-Source EDA for Machine Learning, Tom Spyrou, Precision Innovations Inc: Abstract
This talk addresses the challenges hindering the integration of machine learning (ML) within Electronic Design Automation (EDA) physical design workflows. The scalability of ML-based approaches, particularly for model training and hyperparameter optimization, demands extensive computational resources. The utilization of proprietary EDA tools, often priced at approximately $1 million USD per license, poses significant financial barriers, even for large-scale organizations. Furthermore, restrictive End User License Agreements associated with these tools impede reproducible research by prohibiting the sharing of scripts and results. The absence of standardized metrics for capturing tool output and input data has further hampered the adoption of ML in this domain.

To mitigate these obstacles, we propose leveraging the open-source EDA tool suite, OpenROAD. This tool suite was developed at UCSD utilizing Precision Innovations as the primary industrial developer. This approach eliminates per-run licensing costs, facilitating large-scale ML experiments. OpenROAD's open-source nature also enables the unrestricted sharing of scripts and experimental outcomes, fostering collaboration and reproducibility. Precision Innovations offers support and customization services for OpenROAD while contributing all development back to the open-source repository.

Furthermore, the adoption of the Metrics 2.1 standard for capturing key metrics in a standardized format is advocated. This standard enables seamless data sharing and facilitates the training and optimization of ML models for improved EDA results. This paper demonstrates the potential of open-source EDA and standardized metrics to overcome current limitations and promote the widespread adoption of ML in physical design automation.

Bio

Tom Spyrou is the CEO of Precision Innovation Inc, the primary industrial developer of the OpenROAD EDA tool suite. Tom is a well-known EDA system architect. Before his current position, Tom has worked for over 30 years as an EDA Technologist and has gained extensive experience in areas including Static Timing Analysis, Logic Synthesis, Power Grid Analysis, Database Technology and Floor-planning. He has led the development of leading-edge commercial engines and products such as PrimeTime, Voltage Storm, First Encounter, and the Open Access Database. He was a key architect of timing closure in the Altera Quartus FPGA design tool. Tom has been driving EDA algorithms to utilize parallel programming approaches with both multi-process and multi-threaded techniques. He has a BS from Carnegie Mellon University in ECE and an MS from Santa Clara University
9. Open Source Co-Design of LLMs for the Edge – From Cloud to Handheld – for Ushering in an Era of Localized Intelligence, Gregory Kielian, Google Research: Abstract
The advent of Large Language Models (LLMs) powered by Transformer architectures has ushered in a new era of artificial intelligence. However, the substantial computational and memory demands of these models have largely confined them to the cloud, limiting their deployment on edge-devices and real-time, interactive, and privacy-sensitive applications. To approach the formidable hardware challenge, and unlock potential of LLMs on the edge, we must co-optimize both the model as well as the hardware. For this, OpenROAD and OpenFASOC are critical for providing insight into effects of model changes onto the hardware PPA space, as we co-design a combined HW/SW solution. We showcase concrete examples of this co-design approach, including tackling Softmax bottleneck for long-contexts, and illustrate how both questioning core algorithms and embracing a multidisciplinary mindset can break new ground. Advancing open-source tooling for multidisciplinary hardware-software-model co-design highlights open source's potential to democratize specialized AI hardware design, unlocking new possibilities for AI on the edge and an era of unprecedented real-time interaction and locally-intelligent machines.

Bio

Gregory Kielian leads a multidisciplinary research effort at Google Research focused on enabling transformers and large language models (LLMs) on edge hardware. The team partners closely with experts from academia and industry, exploring the intersection of hardware-software co-design, new ML architectures, and Mechanistic Interpretability, and Linguistics to help democratize access to LLMs and modern AI.
10. Let’s Create an Open-Source MOSbius, Peter Kinget, Columbia University: Abstract
The MOSbius platform allows a student or designer to experiment with IC-style, analog, CMOS circuits at the lunch table. This unique platform uses a custom chip with CMOS building blocks that can be wired on a breadboard or with a programmable on-chip switch matrix. Measurements can be conducted using an affordable, all-in-one, USB lab instrument. Ready-to-go experiments are provided to learners and instructors on https://mosbius.org. The debugging process to bring-up the MOSbius experiments teaches the designer essential lessons that carry over to high performance circuits. The platform is a great tool to learn about chip design before, or alongside with doing custom chip designs. An open-source MOSbius design will expand the access to MOSbius chips and allow the platform to be replicated across various technologies.

Bio

Peter Kinget is the Bernard J. Lechner Professor of Electrical Engineering at Columbia University in New York. His research group focuses on the design of analog and RF integrated circuits and the novel systems or applications they enable in communications, sensing, computing, and power management. He also devotes a lot of his energy to teaching initiatives like https://mosbius.org and https://vlsidesignlab.org
11.Dynamically Pipelined Arithmetic Modules for Adaptive Critical Path Optimization, Ethan Huang and Nealson Li, Georgia Institute of Technology: Abstract
This work presents an ad-hoc retiming engine that leverages dynamically pipelined arithmetic modules to address timing closure challenges in an L2 normalization filter. Implemented entirely using open-source tools and the SKY130 PDK, our approach includes both a custom retiming decision-making algorithm and a library of reconfigurable arithmetic modules.

Bio

Ethan Huang is an incoming sophomore at Georgia Institute of Technology, majoring in Electrical Engineering. He is a Design Verification Lead at SiliconJackets, a student-led organization focused on advancing hands-on experience in chip design and fabrication. Ethan recently co-authored a study titled "Characterization of an 850 nm Power-over-Fiber Converter at Cryogenic Temperatures".

Nealson Li received his B.S. degree in the department of Electrical Engineering from National Cheng Kung University, Taiwan in July, 2016, and M.S. degree in Electrical and Computer Engineering from Georgia Tech, Atlanta, in December 2017. In 2018, he joined Qualcomm, as an ASIC design engineer. He worked on design and verification of last level cache controller for two years. He joined ICSRL in the Fall of 2020 and is currently pursuing his PhD degree in the department of Electrical and Computer Engineering at Georgia Institute of Technology. His research interests include VLSI Circuit and System Design, Wearables, AR/VR and Machine Learning.
12.Automated Flash ADC Generator, Utkarsh Sharma, UCLA: Abstract
Analog-to-Digital Converters have a circuit structure which consists of a unit-cell repeated several times according to the desired resolution. This work exploits this fact and implements an ADC using smaller unit-cells which are further divided into smaller blocks. The blocks are implemented using Glayout (a python based framework) resulting in a highly scalable and distributable design with each block being parameterizable. To demonstrate, a 3b Flash ADC is generated in SKY 130 PDK and then simulated using open-source tools.

Bio

Utkarsh Sharma is a PhD student in the department of Electrical Engineering at UCLA. He received his B.S. degree from MNNIT Allahabad, India and M.S. degree from Texas A&M University in 2017 and 2021 respectively. His research interests include high-speed data converters and wireline transceivers.

2025 Symposium on
VLSI Technology and Circuits

Workshop 7

What is Possible with Open Chip Design? The Journey so Far.

About Organizer