Workshop 4
Innovations and challenges in the Advanced packaging era
Organizer : Angelique Raley (Tokyo Electron Ltd)
In this workshop, we will gather industry leaders in EDA, AI Chip design, semiconductor equipment manufacturer, suppliers to review the recent innovations and trends in advanced packaging and the remaining challenges that need to be overcome across the board to fully leverage the benefits of 3D Scaling
About Organizer
Angélique Raley is currently Director of Technology for integration and 3DI in TEL technology center of America (TTCA) one of the major R&D centers for Tokyo Electron Limited outside of Japan. In her current role she focuses on R&D and integrating TEL’s broad equipment portfolio to deliver differentiated solutions in advanced logic, memory, packaging, and photonics. Prior to this she worked as a plasma etch process development engineer and later led a process development group focusing on EUV patterning technology, multi-patterning, and back end of line scaling for advanced logic before moving into the TEL etch business unit leader role for US based customers. She received her M.S. in materials science and engineering from Polytech’ Grenoble, France and started her career in the semiconductor industry as an integration engineer working for Samsung in flash memory before joining TEL in 2010. Angélique has been an active member of the semiconductor research community and sits on the organizing committee of several international conferences. Throughout her career she has contributed multiple conference papers, several invited talks and over 50 granted patents to the steadfast advancement of key semiconductor technologies.
- 1. 3D Heterogeneous Integration and EDA, Andras Vass-Varnai, Siemens
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Abstract
Advanced 3D IC and heterogeneous integration architectures face critical thermal management challenges due to increased power density and multi-die configurations, particularly in high-performance computing applications where thermal considerations directly impact system reliability.
A unified approach to thermal management enables seamless integration of die-level and package-level thermal analysis throughout the design process. Digital twin methodology facilitates progressive refinement of thermal models, supporting both early feasibility assessment and detailed sign-off analysis. In my presentation I will introduce a workflow that bridges IC design and packaging domains, enabling comprehensive system-level thermal analysis across multiple dies, substrates, and packaging elements.
This integrated methodology allows early evaluation of thermal solutions and supports optimization across the entire heterogeneous system. By combining IC thermal characteristics with package-level analysis, teams can efficiently develop thermal management strategies while fostering collaboration between die designers, package architects, and thermal analysts.
- 2. Co-Packaged Optics: Enabling Scalable and Efficient Interconnects for the Future of Accelerated Computing, Liron Gantz, NVIDIA
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Abstract
The rapid advancements in machine learning, particularly large language models (LLMs), are driving an exponential increase in compute demands, with requirements growing by an order of magnitude approximately every 18 months. Traditional improvements in silicon technology alone are no longer sufficient, prompting a paradigm shift from general-purpose computing to accelerated computing and massive parallelism. As a result, the boundaries between high-performance computing (HPC) and data centers are blurring, with elements like NVIDIA’s DGX SuperPods emerging as fundamental units of compute. This shift amplifies the criticality of interconnect bandwidth, which has become a key bottleneck. Co-packaged optics (CPO) provide a transformative solution, enabling scalable, high-bandwidth, and power-efficient interconnects for future workloads. To fully realize the potential of CPO, we must explore advanced 2.5D and 3D integration schemes that enable further scaling and efficiency.
- 3. Perspectives on Benefits and implementation of 3DI in advanced memory, Masayoshi Tagami, Kioxia
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Abstract
3D stacked devices have been developed and manufactured to realize gains in power, performance, area and cost (PPAC) in various devices. In 3D flash memory, which is applied for Cloud, Big data and AI, CMOS directly bonded to array (CBA) technology has been developed to enhance PPAC. CMOS and memory cell are processed with optimum thermal budget individually and wafer-to-wafer Cu direct bonding process is investigated to obtain robust bonding characteristics between CMOS and memory cell. As a result, CMOS and memory cell performance can be improved, and further 2D and 3D scaling can be achieved. CBA technology is essential to realize PPAC goals for future 3D flash memory.
- 4. Advancing AI Performance: Innovations in 3D Chiplet Platforms and Integration, Kenneth Larsen, Synopsis
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Abstract
Widespread deployment of artificial intelligence systems may require a new class of 3D chiplet platforms with orders of magnitude more performance per unit volume than current technologies. 3D integration has been a critical enabler for addressing challenges in throughput, bandwidth, latency, power efficiency, and thermal management in high-performance computing. Advances in extreme Cu-Cu bond pitch for die stacking, coupled with package-level feature scaling that approaches the top-metal layers of chiplets, unlock fine-grained partitioning of logic and memory. This enables unprecedented computational density, improved energy efficiency, and enhanced interconnecting bandwidth, pushing beyond the limits current state-of-the-art. To maximize the potential of these platforms, methodologies such as Design Space Optimization (DSO) and Technology Co-Optimization (TCO) are essential for evaluating cost, performance, and thermal trade-offs. This presentation will explore recent technological advancements, along with the evolving tools, workflows, and methodologies shaping the next generation of 3D chiplet platforms for AI.
- 5. Progress in Semiconductor equipment development to drive 3DI expansion, Angélique Raley, TEL
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Abstract
While CMOS monolithic scaling continues, the slowdown in power performance area and cost (PPAC) improvement as well as the rise of AI and high-performance computing demand have accelerated the need to implement vertical integration solutions more broadly. 3DI/HI can enable next generation scaling through BSPDN (Backside Power Delivery Network) & sequential CFET in logic, 3D Stacking in NAND flash and multilayer stacking in HBM (High bandwidth memory). In this talk, we’ll discuss the opportunities and challenges associated with hybrid and fusion bonding technology from an equipment standpoint and provide an overview of our current research progress leveraging TEL’s equipment portfolio.
- 6. "Ultra-Dense 3D Heterogeneous Integration: Architectures, System-Level Benefits, and Manufacturing Readiness", Suhyeong Choi, Standford/ SiClarity
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Abstract
N3XT 3D is a disruptive computing systems technology targeting a 1,000× improvement in system-level Energy Delay Product (EDP) for abundant-data applications such as AI/ML. N3XT stands for Nano-Engineered Computing Systems Technology. This talk builds on the foundations of N3XT 3D, exploring its 3D system architecture – integrating heterogeneous memory and logic technologies – to fully leverage the benefits of ultra-dense 3D connections. We demonstrate the significant role of ultra-dense 3D connections in directly yielding large system-level EDP benefits. Early EDA software for analyzing ultra-dense wafer-to-wafer interconnects, demonstrating a path toward high-volume manufacturing readiness, will be presented. Finally, systems that integrate multiple N3XT 3D chips and scale with growing problem sizes — the N3XT 3D MOSAIC -- will be discussed.