Workshop 2
Advanced Heterogeneous System with 3D Chiplet Integration
Organizer : Fumihiro Inoue (YOKOHAMA National University)
Organizer : Takafumi Fukushima (Tohoku University)
Heterogeneous system integration with advanced chiplet architectures has emerged as a key enabler for next-generation devices for AI. This workshop delves into the advanced perspectives and cutting-edge technologies shaping this domain, focusing on critical aspects such as High Bandwidth Memory (HBM), innovative 3D/packaging techniques, and the evolving role of Electronic Design Automation (EDA) tools.
About Organizer
Fumihiro Inoue is an Associate Professor at Yokohama National University and Vice-Director of the Semiconductor and Quantum Integrated Electronics Research Center. Previously, he worked at imec, specializing in unit processes for 3D integration and chiplet until 2021. In recognition of his significant contributions to the field, he received the prestigious IEEE EPS Outstanding Young Engineer Award in 2022.
- 1. Hybrid Bonding Interconnect Pitch Scaling: Wafer-to-Wafer and Die-to-Wafer Cu/SiCN Hybrid Bonding, Eric Beyne, Senior Fellow, Imec
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Abstract:
Hybrid bonding is recognized as the key technology for advanced heterogeneous wafer-level system integration. This is enabled through aggressive pad size and 3D interconnect pitch scaling, resulting in minimal electrical die-to-die interconnect delay. In this presentation we will discuss the properties of SiCN dielectrics as material of choice for hybrid bonding, as well as the process requirements for the mixed Cu/SiCN surface finish of wafers. The physical mechanisms of hybrid bonding will be discussed. The various improvements in wafer processing and wafer alignment and bonding will be discussed, resulting in high yield hybrid bonding down to 400nm interconnect pitch. When applying this hybrid bonding technology to die-to-wafer, additional challenges need to be addressed. Particularly challenging is maintaining the quality and cleanliness of the Cu/SiCN surface through die thinning, singulation and individual die pick & place operations. We discuss a process flow to enable the mitigation of these challenges, demonstrating 2 µm pitch die-to-wafer hybrid bonding. - 2. The Role of EDA as Chips Transform Into 3D Systems, Ksenia Roze, Sr. Software Engineering Group Director, System Design Analysis
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Abstract:
As the electronics industry transitions from Moore’s Law to “More-than-Moore,” we are witnessing a convergence of technologies across ICs, and systems design with increased emphasis on mechanical considerations. This fundamental shift in how we design today’s products requires new advanced design and analysis flows that combine tools across the spectrum of EDA solutions. One of the most critical capabilities of these system-level designs and flows is to enable seamless cross-domain co-design and co-analysis, allowing engineers to achieve the highest performance and lowest cost products. The days of IC and package designers ‘throwing data over the wall’ are over. Heterogeneous Integration (HI) is ushering in a new era of electronic product design with collaboration at its core – one that lives or dies on the seamless interaction between analog/digital IC teams, package design teams, and the electrical/thermal/mechanical modeling and analysis teams, that need to validate these complex 3D systems. The use of advanced packaging technologies to combine smaller, discrete chiplets into one system-in-package (SiP) not only pushes the need for more advanced multi-die packaging but also makes packaging part and parcel of the process. Doing so significantly reduces dependence on Moore’s Law at a time when building advanced monolithic system-on-chip (SoC) is no longer the best option from a cost and technology perspective.
This presentation will describe the challenges engineering teams face when pivoting from monolithic SoC design to 3D multi-die/chiplet package design and how EDA can help address these challenges. - 3. HBM (High Bandwidth Memory) and Advanced Packaging Technologies for AI Era, Kangwook Lee, SVP, Head of PKG Development, SK Hynix
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Abstract:
The semiconductor packaging industry is expected to grow in the coming years, driven by the increasing demands for semiconductor chips in various applications, such as smartphones, autonomous vehicles, 5/6G, high-performance computing, IoT devices, and artificial intelligence. Another trend is the increasing adoption of heterogeneous integration, where different types of chips, such as CPUs, GPUs, and memory, are integrated into a single package to improve performance and reduce power consumption.
To overcome the limitations of performance/power/density/bandwidth of cutting edge systems, and to create new business opportunity and new values, the importance of advanced packaging technologies is more increased. For the above reasons, the future of the semiconductor packaging industry looks promising, with the increasing demand for semiconductor chips in various applications and the emergence of new packaging technologies driving growth and innovation in the semiconductor industry.
Major semiconductor players accelerate the competition to lead semiconductor industry hegemony by the evolution of advanced packaging technology such as chiplets and 2.5D/3D heterogeneous integration.
SK hynix drive the innovation of packaging technology to meet the demand for higher bandwidth and capacity of memory devices requiring in the increased AI workload applications such as the advent of ChatGPT, an artificial intelligence chatbot.
SK hynix’s high bandwidth memory (HBM), offers the largest capacity and bandwidth and also comes with the most improved space/power efficiency enabled by an advanced packaging technology of novel 3D chip stacking, which stacks multiple DRAM chips vertically, enabling faster communication w/ xPUs.
SK hynix is a sole company supplied the entire generation line up after the launch the world’s first HBM in cooperation with AMD in 2013 and continuously released every-generation HBMs (HBM2/HBM2E/HBM3/HBM3E) for the first time in the industry and has secured a market share of 60-70 percent. SK hynix leading the HBM market by outstanding product performance & quality, tech readiness, wide product portfolio, mass production experience and preemptive investment.
The chip-let packaging technology based on heterogeneous integration will be another key driver for memory-centric systems various combinations of logic and memory devices. By the evolution of advanced packaging technologies, SK hynix will continuously lead the competitiveness of memory business and prepare the business innovation for beyond memory era. -
- 4. Chiplet and Heterogeneous integration Technologies for HPC and AI, Katsuyuki Sakuma, IBM
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Abstract:
High Performance Computing (HPC) systems and AI accelerators, while having different computing characteristics and applications, share a common need for higher performance, improved power efficiency, and flexible scalability. Chiplet and heterogeneous integration are gaining attention in both areas as technologies to meet these requirements. Chiplets optimize and partition functional blocks to manufacture chips, which improves chip yield and enables modularization of designs. On the other hand, heterogeneous integration, which integrates these separate chips in a single package at high density, enables flexible functional configurations by integrating heterogeneous devices and contributes to future system scalability. This presentation will start with the background and focus on the progress of 3D integration, which is the core of heterogeneous integration, and review the process, implementation issues, and experimental results of hybrid bonding technology, which enables higher density and lower power in die-to-die interconnections in particular.