Workshop 12
Chip tapeout classes: Methodologies, technologies and outcomes
Organizer :Borivoje Nikolic (University of California) VLSI design classes, in which students design chips and send them out for fabrication in one term, were immensely popular in the 1990's in universities worldwide, but their offering faded away in 2000's. This decline was due to the increase in process and design complexities, chip turnaround times and challenges in accessing design tools and infrastructure. Recent years have seen a revival of classes that feature practical chip design, where several universities have offered such classes that resulted in successful class chip tapeouts. These classes were based on a different technologies (ranging from 180nm to 16nm), tools (commercial and open-source) and methodologies. There is a growing interest in the outcome of these classes, and possible adoption in other universities, but their approach and content is not widely discussed, except for a few articles in the IEEE Solid-State Circuits Magazine. The past two workshops at VLSI on Open-Source Design featured presentations from the University of Tokyo, Purdue University and eFabless corp on class tapeouts, but the actual state of course offerings is much broader.
Borivoje Nikolic (Fellow, IEEE) received the Dipl.-Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Belgrade, Serbia, in 1992 and 1994, respectively, and the Ph.D. degree from the University of California at Davis, Davis, CA, USA, in 1999.|In 1999, he joined the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA, where he is currently a professor and holds a National Semiconductor Distinguished Professorship in Engineering.
This talk will describe the special topics tapeout and bringup courses taught at the University of California Berkeley, in which mostly undergraduate students designed and sent out for fabrication multiple SoCs in the past four years in Intel 16 process technology. These SoCs include multi-core RISC-V processors with custom accelerators, a memory system and standard peripherals. If space allows, chips running machine-learning and audio applications will be demonstrated by the past students in the class
Since 2014 I have offered the VLSI Design Lab course six times at Columbia University. It is designed to fit in a three-semester M.S. program, and it offers students the satisfaction of designing their own IC that they can interact with in an application. Students define an IC from scratch, design, simulate, and lay it out in the spring; the chip is fabricated in summer, and brought up and demonstrated in the application in fall. More than 140 students have taped out over 55 chips. Popular designs include class-D amplifiers, PPG monitors, digital clocks, ultrasound transceivers, but also include a RISC-V processor, neural processing units, an FPGA, ADCs and RF circuits. The lab gives the student a holistic experience not only of the chip design process, but also of integrating the chip in an application.
Designing high performance and energy efficient accelerators requires significant engineering effort, and as the rapidly evolving field of machine learning develops new models, the current approach of designing ad hoc accelerators does not scale. In this talk, I will present our ongoing research on a high-level synthesis (HLS) based framework for exploration and agile design of hardware accelerators for AI. Given architectural parameters, such as datatype, scaling granularity, compute parallelism and memory sizes, our framework quickly generates a performant fabrication-ready accelerator. I will detail how we are using this framework together with mflowgen, an agile physical design flow generator, to design chips in mere ten weeks in Stanford’s tapeout class.
The one-semester course introduces junior/senior-level undergraduate students to System-on-Chip (SoC) design principles, electronic design automation (EDA) tools
(e.g., Chipyard, Cadence, Synopsys, Siemens), and how to use them to take a design from RTL to GDSII culminating in a chip tape out using Intel 16nm FinFet technology.
The purpose of this workshop is to bring together the community of educators and designers that would present and discuss the current state of tapeout classes in an open forum. If the time permits, there would be a panel discussion and if the space allows, there will be student project demonstrations. We have several participants confirmed, that include Priyanka Raina (Stanford University), Peter Kinget (Columbia University), Kevin Kornegay (Morgan State University), Ken Mai (Carnegie Mellon University), Matt Morrison (University of Notre Dame) and Vikram Jain and Borivoje Nikolic (University of California, Berkeley). We are interested in including views from Behzad Razavi (UCLA), Boris Murmann (University of Hawaii), Mototsuku Hamada or Makoto Ikeda (The University of Tokyo), Chris Torng (University of Southern California), David Junkin (Cadence) and eFabless (Mohammed Kassem). Additionally, we would like to include testimonials and suggestions for future classes from companies who have hired students from these classes (e.g. Jared Zerbe from Apple, or Ben Keller from NVIDIA), possibly during the panel discussion. We do realize that this agenda may be too broad for one workshop, so it is possible to have multiple offerings at future VLSI Symposia, as there is a growing interest in this topic from both the educators and employers in the VLSI community.
About Organizer
Dr. Nikoli? received the NSF CAREER Award in 2003, the College of Engineering Best Doctoral Dissertation Prize, the Anil K. Jain Prize for the Best Doctoral Dissertation in Electrical and Computer Engineering at the University of California at Davis in 1999, and the City of Belgrade Award for the Best Diploma Thesis in 1992. in 2024, he won the IEEE Solid-State Circuits Society's Innovative Education Award for the development of tapeout classes. For work with his students and colleagues, he has received the best paper awards at the IEEE International Solid-State Circuits Conference, the Symposium on VLSI Circuits, the IEEE International SOI Conference, the European Solid-State Device Research Conference, the European Solid-State Circuits Conference, the IEEE Custom Integrated Circuits Conference, the S3S Conference, the Design Automation Conference, and the ACM/IEEE International Symposium of Low-Power Electronics.
From 2014 to 2015, he was a Distinguished Lecturer of the IEEE Solid-State Circuits Society. He was a Technical Program Chair for the 2022 Symposium on VLSI Technology and Circuits, and a General Chair for the 2024 IEEE Symposium on VLSI Technology and Circuits.
Students will 1) build ARM, RISC-V, and AI/Cryptography accelerator processors; 2)build interfaces such as USB, URAT, and JTAG interfaces; and 3) determine system|power, performance, and area while developing an intuition for the trade-offs between these parameters for optimization. We will present several design examples.