Symposium on VLSI Technology and Circuits

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Chip tapeout classes: Methodologies, technologies and outcomes

Organizer :Borivoje Nikolic (University of California)

VLSI design classes, in which students design chips and send them out for fabrication in one term, were immensely popular in the 1990's in universities worldwide, but their offering faded away in 2000's. This decline was due to the increase in process and design complexities, chip turnaround times and challenges in accessing design tools and infrastructure. Recent years have seen a revival of classes that feature practical chip design, where several universities have offered such classes that resulted in successful class chip tapeouts. These classes were based on a different technologies (ranging from 130nm to 16nm), tools (commercial and open-source) and methodologies. There is a growing interest in the outcome of these classes, and possible adoption in other universities, but their approach and content are not widely discussed.

The purpose of this workshop is to bring together the community of educators and practicing designers that would present and discuss the current state of tapeout classes in an open forum.

About Organizer

　Borivoje Nikolic is a Professor in the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA, where he holds a National Semiconductor Distinguished Professorship in Engineering. He is　interested in agile design of digital and mixed-signal systems on a chip, and systems in a package. He is a past Chair of the Symposium on VLSI Technology and Circuits.

1. Opening, Borivoje Nikolic, University of California, Berkeley
2. Creating Agile Chip Design Flows Using High-Level Synthesis and Mflowgen, Priyanka Raina, Stanford University: Abstract
Designing high performance and energy efficient accelerators requires significant engineering effort, and as the rapidly evolving field of machine learning develops new models, the current approach of designing ad hoc accelerators does not scale. In this talk, I will present our ongoing research on a high-level synthesis (HLS) based framework for exploration and agile design of hardware accelerators for AI. Given architectural parameters, such as datatype, scaling granularity, compute parallelism and memory sizes, our framework quickly generates a performant fabrication-ready accelerator. I will detail how we are using this framework together with mflowgen, an agile physical design flow generator, to design chips in mere ten weeks in Stanford’s tapeout class.

Bio
Priyanka Raina is an Assistant Professor of Electrical Engineering at Stanford University. She received her BTech in Electrical Engineering from IIT Delhi in 2011 and her SM and PhD in Electrical Engineering and Computer Science from MIT in 2013 and 2018. Her research is on domain-specific hardware accelerators and agile hardware-software co-design.
3. Chip Design Flows Using Commercial Tools in Cloud-Based Classroom Environments, Matthew Morisson, University of Notre Dame: Abstract
Integrating EDA tools and flows in undergraduate circuit design courses capable of reliable, affordable, and replicable chip tapeouts is a critical barrier to training the next generation of semiconductor researchers, engineers, and technicians. The tool flows whose usage would make students competitive are sophisticated and expensive, requiring thousands of commands, as well as concerns about script sharing and export controls, all of which are prohibitive of widespread adoption of commercial EDA as well as advanced PDKs in class-to-fab contexts. These challenges are acutely felt at universities with limited chip design experience. In this presentation, we will present the results of an undergraduate tapeout course - the first of its kind at a U.S. Historically Black College and University, where nine students completed a tapeout in 8 weeks using commercial EDA tools using a secure chamber allowing remote access and instruction, including RTL design and synthesis, advanced test pattern generation, place and route, pad ring generation, DRC/LVS/Extraction, and verification. We will then present a High-Level Synthesis flow leveraging SystemC to generate RTL as an input to the RTL-to-GDSII flow.

Bio
Matthew Morrison is an Associate Teaching Professor in the Department of Computer Science and Engineering at the University of Notre Dame. At Notre Dame, he conducts curriculum development in digital integrated circuit design and high-performance space computing. He promotes semiconductor education initiatives throughout the United States, including serving as a visiting professor at Howard University, on the governing board of the Center for Education of Microelectronic Designers, and as a visiting researcher with Google Custom Silicon.
4. Three Chips in a Semester, Borivoje Nikolic and Vikram, Jain, University of California, Berkeley,: Abstract
This talk will describe the special topics tapeout and bringup courses taught at the University of California Berkeley, in which mostly undergraduate students designed and sent out for fabrication multiple SoCs in the past four years in Intel 16 process technology. These SoCs include multi-core RISC-V processors with custom accelerators, a memory system and standard peripherals. On Monday evening, during the demo session, a class chip that runs running machine-learning and audio applications will be demonstrated by the past students in the class.

Bio
Borivoje Nikolic is a Professor in the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA, where he holds a National Semiconductor Distinguished Professorship in Engineering. He is interested in an agile design of digital and mixed-signal systems on a chip, and systems in a package.
5. Anatomy of an Undergraduate SoC Tape Out Class, Kevin Kornegay, Morgan State University: Abstract
The one-semester course introduces junior/senior-level undergraduate students to System-on-Chip (SoC)design principles, electronic design automation (EDA) tools (e.g., Chipyard, Cadence, Synopsys, Siemens), and how to use them to take a design from RTL to GDSII culminating in a chip tape out using Intel 16nm FinFet technology. Students will 1) build ARM, RISC-V, and AI/Cryptography accelerator processors; 2) build interfaces such as USB, URAT, and JTAG interfaces; and 3) determine system power, performance, and area while developing an intuition for the trade-offs between these parameters for optimization. We will present several design examples.

Bio
Kevin T. Kornegay is the Eugene DeLoatch Endowed Professor and Director of the Cybersecurity Assurance and Policy (CAP) Center at Morgan State University in Baltimore, MD. His research interests include hardware assurance and system-on-chip (SoC) design He serves on the technical program committee of several international conferences such as the IEEE Symposium on VLSI Technology, Circuits, and Systems.
6. Balancing Creative Freedom and Success Rate via Standardization in a Tapeout Course Sequence, Ken Mai, Carnegie Mellon University: Abstract
Abstract: This talk will give an overview of the CMU tapeout course sequence, show our results to date, and discuss how the course has evolved over the past few years. The main driver for evolution has been the need to balance student creative freedom and tapeout/testing success rate. We strive to allow the students as many degrees of freedom in the design as possible, while providing them enough guard rails to avoid common pitfalls and minimize effort spent "reinventing the wheel." Particularly the design of I/O interfaces and on-die testing infrastructure can consume scarce engineering resources and introduce unnecessary risk of bugs. Thus, we have implemented a set of modular interface and testchip infrastructure IP to enhance the design, verification, and testing of testchips in classroom and academic research environments.

Bio
Ken Mai is a Principal Systems Scientist in the Electrical and Computer Engineering Department at Carnegie Mellon University. He received his BS, MS, and PhD degrees from Stanford University. His research interests include VLSI design, reconfigurable computing, hardware security, and microelectronics for austere environments.
7. From Schematic to Silicon: ADC Tapeout in 10 Weeks, Drew Hall, University of California, San Diego,: Abstract
This talk presents a two-quarter, team-based course sequence offered at the University of California, San Diego, in which students gain hands-on experience with the full lifecycle of CMOS chip design, from physical design and tapeout to post-silicon validation. In the first quarter, students work in teams to lay out a 9-bit asynchronous SAR ADC, while learning key concepts such as process variation, matching techniques, parasitics, and digital synthesis. The course uses Cadence tools and a TSMC 65nm CMOS process, exposing students to industry-standard design flows. Students complete the full physical design toolchain, including design rule checking (DRC), layout versus schematic (LVS) verification, and parasitic extraction (RCX). Formal design reviews allow students to receive iterative feedback from instructors, industry leaders, and peers at key milestones in the design flow. Fabrication occurs over the summer, and in the second quarter, students design printed circuit boards (PCBs), write automation scripts for instrumentation and data analysis, and characterize their fabricated chips. Offered five times to date, the course has enabled over 200 students -- many of them undergraduates -- to complete a tapeout and measurement cycle, providing practical, end-to-end experience in modern VLSI design. This model has proven to be scalable and could serve as a template for similar courses at other institutions seeking to reintroduce tapeout experiences into their curricula.

Bio
Drew A. Hall is a Full Professor in the Department of Electrical and Computer Engineering at UC San Diego, where he leads research in bioelectronics, biosensors, and analog circuit design. Prior to joining UCSD, he was a Research Scientist in the Integrated Biosensors Laboratory at Intel and completed his PhD at Stanford University. He has served on the ISSCC and CICC Technical Program Committees and as an Associate Editor for multiple IEEE journals.
8. Industry announcements and Q&A, Demos: At Monday’s reception

2025 Symposium on
VLSI Technology and Circuits

Workshop 12

Chip tapeout classes: Methodologies, technologies and outcomes

About Organizer