Workshop 10
Advancing Neuromorphic Technology Research and Commercialization: From Sensors to Edge to Cloud
Organizer :Xabier Iturbe (IKERLAN Research Centre)
This workshop will explore advanced approaches to neuromorphic and AI sensing and computing in Europe, enabled by emerging VLSI technologies such as silicon photonics and 3D silicon integration. It will showcase innovative in-sensor and in-memory architectures that combine analog, digital, and optical processing, and exploit sparsity in both standard and novel event-based sensors inspired by insect and vertebrate vision, achieving ultra-low power and latency. The workshop will feature talks on groundbreaking research from EU-funded projects with budgets between 3 and 10 million euros and TRLs of 3 to 6 (i.e., proof of-concept to pre-commercial grades), as well as commercial chips from European deep-tech spin-outs built on EU-funded research, including the flagship Human Brain Project. Finally, the featured talks will also cover pre-commercial and commercial neuromorphic chips and architectures designed by large companies with strong European presence in Europe, including IBM, Snap and Hewlett Packard. By bringing together leading academic institutions and technology companies, the workshop will present key research directions and technology roadmaps poised to drive the next wave of neuromorphic A powered applications– from sensors to cloud– including augmented reality (AR), ambient intelligence, and physical AI-enabled robotics, among others. This workshop aims to strengthen collaboration between organizations in the EU and Asia, particularly in Japan, South Korea and Taiwan, for the research, design, and manufacturing of neuromorphic and AI chips using advanced VLSI technology.
Topics & potential presentation segments
The workshop showcases implementations of novel neuromorphic concepts using CMOS, silicon photonics and analog in-memory technology as well as state-of-the-art commercial silicon products, with potential impact in several segments addressed by the 2025 Symposium on VLSI Technology and Circuits, including AI/ML, Augmented reality (AR), Robotics & Physical AI, AIoT & Ambient intelligence.
Strcture
The workshop features 10 talks, each lasting 15 or 20 minutes, followed by a 25-minute Q&A session, for a total duration of 180 minutes. The talks are divided into five thematic blocks, each focusing on VLSI technology areas relevant to neuromorphic and AI sensor and processor chips:
– Talk 2 (15 mins): MISEL EU project (https://www.misel-project.eu)
– Talk 3 (15 mins): InsectNeuroNano EU project (https://www.insectneuronano.lu.se)
– Talk 5 (15 mins): Hewlett-Packard Labs (https://www.hpe.com)
– Talk 7 (15 mins): Innatera Nanosystems B.V. (https://innatera.com)
– Talk 9 (15 mins): Snap Inc. (https://www.snap.com)
- 1. Novel neuromorphic visual perception modalities to enable physical AI, Xabier Iturbe, IKERLAN Technology Centre
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Potential presentation segments:
Smart sensors for robotics and physical AI.
Abstract:
The emergence of heterogeneous integration and the era of chiplets, accelerated by the adoption of Universal Chiplet Interconnect Express (UCIE) has significantly increased the demand for higher connection density and bandwidth, lower latency and modular die sizes in a single package. Die-to-wafer (D2W) hybrid bonding has become a key contender in addressing this demand by directly bonding logic/memory die onto a target wafer. However this technology presents new challenges in precision placement and interface material interaction. This talk will demystify D2W bonding from the perspective of a high throughput, high accuracy bonder as well as real world findings and key performance factors. - 2. MISEL: a multiband event-based intelligent vision system, Jacek Flak, VTT Technical Research Centre of Finland Ltd.
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Potential presentation segments:
Smart sensors for robotics and physical AI.
Abstract:
MISEL is a visual cognition system which employs in- and near-sensor neuromorphic computing. It consists of two subsystem chips fabricated in 180nm CMOS technology. Cellu lar/cerebellar sensor-processor is a 100 million transistor system-on-chip that includes a 640x480 sized always-on CMOS photodetector array providing gray-scale image data as well as complex events. The on-chip mixed-mode processing paths comprise both spatial and temporal computing resources capable of making instant reflex-type decisions. The chip also comprises separate readout circuits for the colloidal quantum dot (CQD) sensor monolithically post-processed in back-end of line (BEOL) to extend the system perception abilities into infrared range (∼1500 nm). The second chip (cortical processor) provides functionality associated with visual cortex such as a selection of region of interest and analysis of image data. The processing is based on in-memory computing of data encoded in hyperdimensional vectors. It relies either on CMOS memories or ferroelectric memories monolithically post-processed in BEOL. This talk will introduce the MISEL concept and its VLSI implementation including overview of the BEOL processes as well as the performance achieved in the test measurements. - 3. Nanophotonic neuromorphic computing and sensing: Broadcasting networks of nanoscale neural nodes that receive, transmit, and analyze light signals, Anders Mikkelsen, Lund University
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Potential presentation segments:
Sensors and edge AI for autonomous navigation, environmental sensing, and manufacturing.
Abstract:
InsectNeuroNano develops and investigates nanophotonic on-chip devices for integrated sensing and neural computation, inspired by the insect brain. Central is the availability of highly efficient and multifunctional III-V semiconductor nano-optoelectronic components as well as nanophotonic light guiding concepts that can implement insect inspired neuromorphic circuits. As proof of concept, we target the complete pathway from polarized light sensing in the insect eye to the internal compass and memory circuits by which this information is integrated in a continuous accurate estimate of location. Building on verified biological models, we find that the computational principles can be implemented by broadcasting overlapping light signals in embedded nanoscale networks, with high error tolerance and orders of magnitude better energy and spatial footprint than present technologies. We explore neuromorphic memory functionalities from reversible photoresponsive molecules placed in between the neural nodes. The same nanostructures used for computing can be used for optical sensing, and thus they can act as an integrated sensor and information processing array to extract global orientation information. The long-term goal is to develop an energy-efficient, robust chip that enables autonomous vehicle and robot navigation without the need for GPS. However, the innovative neural components can also be reconfigured into a variety of circuits to address other critical tasks. This technology platform is compatible with silicon CMOS, providing a scalable pathway for future advancements. - 4. Low-power and secure photonic accelerators based on augmented silicon photonics platforms, Fabio Pavanello, CROMA, CNRS
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Potential presentation segments:
AI, ML, IoT, edge computing, circuits for security and secure circuits.
Abstract:
In this talk, a novel approach for photonic accelerators addressing edge computing will be presented alongside some of the most recent results obtained within the framework of the Horizon Europe Neuropuls project. Specifically, an augmented 300-mm wafer CMOS-compatible platform to develop high-performance photonic building blocks will be showcased where phase-change and III-V materials are integrated in a monolithic manner. Such a platform is instrumental to achieve novel functionalities like ultra-low-loss non-volatile neural weights and plastic synapses. Photonic architectures benefiting from the enhanced building blocks will be introduced highlighting their advantages compared to more classical approaches and how strong security layers can be built by leveraging the technology already available for the accelerator. Finally, a gem5 simulation framework to model the RISC-V-interfaced photonic accelerator and extract key metrics such as reliability, power consumption, and latency will be discussed alongside the use-cases targeted by our accelerator. - 5. Integrated photonics for hardware accelerators and neuromorphic computing, Matˇej Hejda, Hewlett-Packard Labs (HPE)
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Potential presentation segments:
Circuits and systems for LLM inference, AI/ML, IoT.
Abstract:
Photonics-powered neuromorphic processors represent one of the promising novel approaches for energy-efficient, next generation AI hardware. However, while the field is currently undergoing a rapid growth, we are still primarily in the nascent (lower TRL) phase of achieving practical optical computing, where current scientific works mainly focus on individual levels of functional abstraction, such as photonic devices or circuits. In Hewlett Packard Labs, we are actively exploring optics-enabled, application-specific solutions for computing and interconnects based on various large scale integrated photonic technologies, such as CMOS-compatible silicon photonics. We have proposed novel devices, such as integrated optical memristors; photonic circuits for highperformance matrix-vector multiplication (MVM) engines, content-addressable memories (CAMs) and chip-scale, high-performance interconnects; scalable architectures for neuromorphic photonic systems; hardware-software co-design methods for resource-constrained photonic chips, and simulators for heterogeneous, photonic-electronic system-level modelling and benchmarking. Recently, we have numerically evaluated interferometric photonic integrated circuits (PICs) as building blocks of optoelectronic neural networks (ONNs) with component-aware training, and demonstrated an implementation of practical, IoT-focused use-cases (such as network intrusion detection) on realistic ONNs. - 6. Heterogeneous neural processing units leveraging analog in-memory computing for edge AI, Irem Boybat, IBM Research Europe- Zurich
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Potential presentation segments:
AI/ML, AI hardware, edge computing, in-memory computing.
Abstract:
The data-intensive and highly parallel compute demands of AI models have driven the integration of specialized Neural Processing Units (NPUs) into System-on-Chip devices for edge AI applications. Analog In-Memory Computing (AIMC) offers a promising approach by co-locating memory and computation, enabling notable energy efficiency improvements. This talk will present an embedded NPU architecture for deep learning inference, tailored to meet the stringent energy, area, and cost constraints of edge AI. The heterogeneous architecture combines digital and analog accelerator nodes to support diverse operation types and precision requirements. AIMC tiles leveraging Phase-Change Memory (PCM) are employed for energy-efficient matrix-vector multiplications while supporting a high non-volatile on-chip weight capacity. Complementing this, a digital data path and programmable software cluster provide flexibility and enable end-to-end inference across multiple precision levels. The discussion will also address the challenge of preserving high accuracy in AIMC-based acceleration, focusing on offline training techniques and efficient mapping strategies. - 7. Innatera’s Spiking Neural Processor (SNP): mixed-signal MCU for power constrained tiny ML applications, Petrut Bogdan, Innatera Nanosystems B.V.
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Potential presentation segments:
Systems for tinyML and Edge AI, Smart sensors, AIoT, Ambient Intelligence.
Abstract:
Ambient intelligence, or pervasive computing, imposes strict system-level constraints and challenges due to sensors and compute units being placed in hard-to-reach or hidden locations, including low-bandwidth communications used sparingly, poor thermal management, and limited battery capacity. Innatera’s Spiking Neural Processor (SNP) is a mixed-signal, heterogeneous SoC designed to efficiently handle a wide range of tiny ML and edge AI workloads in ambient intelligence applications that perform complex tasks directly at the sensor edge with minimal energy usage. The SNP utilizes a mixed-signal Spiking Neural Network (SNN) accelerator that combines analog and digital neurons in the same computational fabric, enabling ultra-low power SNN inference characterized by aggressive quantization, temporal integration and activation sparsity. This talk will explore the design and functioning of these mixed-signal SNN accelerators, along with the DSP and CNN accelerators integrated into Innatera’s SoC, as well as the software toolchain that optimizes their joint operation to achieve system-level benefits. It will also cover the creation, optimization, and deployment of sensor processing pipelines, from data acquisition and pre-processing to inference execution. - 8. A 3D integration technologies for neuromorphic systems, Geert Van der Plas, Imec
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Potential presentation segments:
System integration including HBM, Packaging and EDA tools.
Abstract:
3D integration technologies such as Si interposer and die-to-wafer hybrid bonding have seen wide adoption in industry, especially in high-performance and AI systems. In this talk an overview of 3D integration technologies for advanced systems will be presented. The current stateof-the-art of 3D stacking will be reviewed and a projection of future trends will be shared in the form of a 3D research roadmap. Scaled interconnect pitches at wafer and die level, combined with aggressively scaled through silicon interconnect will enable advanced chiplet and 3D system on chip implementations. With these low parasitic interconnects circuits can communicate seamlessly between tiers. Remaining challenges will be brought to attention such as how to effectively design these systems. We will show how future neuromorphic systems stand to benefit from 3D integration technologies. - 9. Expanding edge AI for wearable augmented reality (AR) with 3D silicon integration, Orlando Moreira, Snap Inc.
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Potential presentation segments:
Augmented reality (AR).
Abstract:
Emerging trends in AI are driving significant changes in the realm of wearable augmented reality (AR) devices, with silicon 3D integration technology playing a key role in this transformation. This talk explores how the roadmap for edge AI converges with silicon 3D integration to empower the next generation of wearable AR applications. In the next few years, wearable AR devices will not only enhance mainstream AI-driven computer vision tasks– such as object recognition, ego pose prediction, keypoint detection, depth perception, and segmentation–, but also expand into new domains like natural language processing, super-resolution and and image/3D model generation. These advanced applications will demand the use of more powerful AI models, such as Transformers, and larger neural networks, requiring significantly higher computational capacity and more parameters than current models. At the same time, constraints such as latency, form factor, power consumption, and thermal envelope will become even more critical as devices must become smaller, lighter, and more efficient. Silicon 3D integration offers a promising solution to address these constraints and achieve higher computational and memory density in an energy-efficient manner. More importantly, the SoC design flexibility in terms of modularity and form factor that it will enable will be critical for addressing application requirements and product constraints. Through examples and forwardlooking insights, this talk will explore how silicon 3D integration can help realize the next phase of wearable AR innovation. - 10. Scaling up neuromorphic computing to cloud-level, Matthias Lohrmann, SpiNNcloud Systems GmbH
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Potential presentation segments:
Circuits and systems for LLM inference, AI/ML.
Abstract:
Unlike traditional computing systems, the brain achieves an unmatched level of energyefficiency by operating asynchronously with its workload driven by neural activity. However, simulating the brain is a highly complex endeavor, limited not only by computational power but also by the intricacies of connectivity and spatiotemporal communication dynamics. This talk will explore the challenges and insights gained from developing a scalable brain-inspired supercomputer, SpiNNcloud, capable of simulating a significant fraction of the human brain in real-time. The talk will begin with an in-depth exploration of the design and functionality of SpiNNcloud’s core building block: the SpiNNaker2 chip. This chip features 152 Arm Cortex M4 cores coupled with accelerators, which can handle up to 1,000 neurons and 1 million synapses per core. The cores are interconnected by means of a lightweight NoC with a Globally Asynchronous Locally Synchronous (GALS) topologythat allows for fine-grained power management, event-based operation, and sparse communication. The talk will then review the strategies for scaling across multi-chip configurations incorporating up to 65,000 SpiNNaker2 chips to deliver cloud-scale real-time performance with high energy-efficiency. Finally, the talk will highlight a number of commercial cloud applications that can benefit from the energy- efficiency and speed of the SpiNNcloud neuromorphic architecture, including LLM inference, optimization solvers, and drug discovery.