Symposium on VLSI Technology and Circuits

Centennial Anniversary of FET Invention: Past, Present, and Future

Organizer : Bin Zhao (IEEE EDS), Tsunenobu Kimoto (JSAP), Kazuhiko Endo (Tohoku Univ.), Yoshihiro Hayashi (AIST), Hiroshi Iwai (NYCU/Sci. Tokyo)

Purpose of the workshop
Since 2023, AI has been widely adopted as a practical tool, driving an explosive demand for high-performance, large-scale GPUs and memory. The foundation of AI's advancement lies in the remarkable evolution of CMOS VLSI technology, which, in turn, is built upon the continuous progress of MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) technology. The concept of the Field-Effect Transistor (FET) dates back to 1925, when J. Lilienfeld first invented the MESFET (Metal-Semiconductor FET) using a Schottky gate. The insulated-gate MOSFET was conceived in 1928, but at the time, the available technology and understanding were insufficient to control current flow along the semiconductor surface. As a result, it took 35 years before a functional transistor-like operation was achieved. The first operation of MOSFET using bulk silicon was presented at a conference in 1960, but with the Bipolar Junction Transistor (BJT) at its peak, expectations for the FET remained low. It took another decade to resolve reliability challenges, allowing FETs to gain market acceptance as LSI (Large-Scale Integration) technology in the early 1970s. Since then, MOSFET LSI has continuously pushed past limitations, undergoing relentless miniaturization—from 10 μm technology in 1970 to an astonishing 2 nm today. This progress has been instrumental in enabling AI and has driven transformative technological shifts across multiple eras, including calculators, personal computers, digital cameras, smartphones, and artificial intelligence. Additionally, the horizontal expansion of FET technology into power devices and image sensors has significantly impacted society. In 2025, we celebrate the 100th anniversary of the FET’s invention. To honor this milestone, we plan to hold a workshop that will reflect on the history of FET development, assess its current state, and explore its future trajectory. We also aim to document its present applications and societal impact, creating an archive that will serve as a reference for the next major milestone in semiconductor innovation.

Date & Time: Sunday, June 8,　13:00-16:15
Room: Shuju II & III, 2nd Floor, Rihga Royal Hotel, Kyoto, Japan

13:00 - 13:05 Opening Remark : Kazuhiko Endo (Program Chair, 2025 Symp. on VLSI,Tohoku Univ.): Abstract:
We are very pleased to host the FET 100 workshop at 2025 VLSI Symposium in Kyoto. FETs have made unimaginable progress in the past 100 years, and now FETs are being manufactured with advanced single-digit nanometer technology. It is very meaningful and exciting to look back at the history of FETs here in 2025 VLSI Symposium on Technology and Circuits.

Biography

Kazuhiko Endo received Ph.D. degrees in electrical engineering from Waseda University, Tokyo in 1999. In 1993, he was with Silicon Systems Research Laboratories, NEC Corporation. In 2004, he joined National Institute of Advanced Industrial Science and Technology (AIST) where we worked on advanced nanodevices. In 2022, he joined Institute of Fluid Science, Tohoku University as a faculty member. He is a program chair of 2025 VLSI Symposium on Technology and Circuits.
13:05 - 13:15 Remark on FET100 : Bin Zhao (President, IEEE EDS): Abstract:
The field-effect transistor (FET), first patented by Julius Lilienfeld in 1925, has profoundly shaped the trajectory of modern electronics and global technological progress. As the FET reaches its 100th anniversary in 2025, we would like to reflect on its historical significance, its evolution into one of the most ubiquitous components in integrated circuits and electronics, and its continuing role in enabling innovations across computing, communications, energy, healthcare, and beyond. It is a moment to review and highlight how the FET has transformed industries and empowered generations of researchers, engineers, and technologists to push the limits of what is possible for humans. This key milestone in modern electronics underscores the importance of sustained collaboration, curiosity, and creativity in advancing semiconductor technologies. More than a celebration, the centennial of the FET is a call to look forward - to inspire new ideas, address emerging challenges, and shape the next century of technological advancement.

Biography

Bin Zhao received his Ph.D. from Caltech and has held engineering and management positions at SEMATECH, Rockwell, Conexant, Skyworks, Freescale, Fairchild, and ON Semiconductor, working on advanced VLSI technology and designing analog/mixed-signal, power management, and RF IC products. In 1997, he developed the industry’s first Cu/SiOCH-based low-k dual-damascene interconnect, now widely used in today’s IC products.
As an engineering director at Freescale, Fairchild, and ON Semiconductor, he led IC product development for consumer electronics, bringing many products to market. He has served as CEO of Everbright Envirotech, the R&D branch of Everbright Environment, a company with multi-billion-dollar revenue in environmental business. He has authored or coauthored 200+ journal publications and conference presentations, written three book chapters, and holds 100+ issued patents. He is an IEEE Fellow and was Founding Co-Chair of the Technical Working Group of RF and Analog/Mixed-Signal Technologies for the International Technology Roadmap for Semiconductors (ITRS).
13:15 - 13:55 Overview - FET History, Present and Future : Hiroshi Iwai (NYCU/Institute of Science Tokyo): Abstract:
Since the first invention of the Field Effect Transistor (FET) with a semiconductor thin-film channel and Schottky gate in 1925, several individuals independently developed FETs and conducted experiments. However, they were unable to achieve satisfactory transistor performance. During these experiments, the operation of the junction transistor was accidentally discovered in 1947, leading to the invention of the pn-junction transistor (Bipolar Junction Transistor, BJT) in 1948. By the mid-1950s, BJTs became widely used in amplifiers and computers, while interest in FETs declined. In 1960, Bell Labs announced the successful operation of MOSFETs, which utilized bulk silicon, an inversion channel, pn-source and drain junctions, and thermally grown SiO₂ gates. However, due to various challenges, MOSFETs did not achieve widespread adoption until the introduction of MOS LSI in the early 1970s. Subsequently, MOSFETs were primarily used for high integration but lower performance, whereas BJTs were preferred for high performance but lower integration. However, in the late 1990s, as miniaturization progressed, the gate length of MOSFETs became smaller than the base width of BJTs, enabling MOSFETs to surpass BJTs in performance. As a result, MOSFETs found applications across a wide range of fields, including high-performance and high-integration systems using CMOS VLSI. This presentation will explore the history of MOSFET development, leading to today's ultra-high integration and ultra-high-performance Nano-CMOS technology, and examine its social impact.

Biography

Hiroshi Iwai is a semiconductor device engineer who has contributed to the advancement of LSI products and technologies for over 50 years. He has held key positions at Toshiba Corporation, Tokyo Institute of Technology, and National Yang Ming Chiao Tung University. He received BE and Ph.D. degrees from the University of Tokyo. At Toshiba, he developed the first NMOS LSI technology, as well as the 1K-bit SRAM and 64K-bit DRAM products.
In 1993 and 1994, he pioneered sub-50 nm CMOS technology—two generations ahead of competitor companies. In the mid-1990s, he developed RF CMOS technology, achieving record-high fT and fmax values, which contributed to the advancement of Bluetooth technology. Dr. Iwai is an Eminent Lecturer for the IEEE Electron Devices Society and has served as IEEE EDS President and IEEE Division I Director. He is a Life Fellow of IEEE and ECS, as well as a Fellow of IEEJ, JSAP and IEICE.
13:55 - 14:35 Structural Evolution and Functional Integration of FETs Traced in a Public Semiconductor Roadmap and the Future Prospectives : Yoshihiro Hayashi (AIST): Abstract:
Based on IEEE International Roadmap for Systems and Devices (IRDS), which is collaborative activities with the Systems and Devices Roadmap Committee of Japan: SDRJ and SiNANO (EU), the structural evolutions and functional integrations in logic LSIs are reviewed. Here, some technological topics will be revisited on the development pathways from the budding stages to be matured: (1) GAAFET with HKMG stacks, (2) 3D integration and (3) low-k/Cu BEOL module with BEOL FETs, etc. Future prospects on the FET integration are also discussed regarding some on-coming markets such as high-speed telecommunications and mobile robotics and sensors.

Biography

Yoshihiro Hayashi received his Ph.D. (Applied Chemistry) from Keio University in 1987. He is currently an Invited Senior Researcher in Semiconductor Research Center at the National Institute of Advanced Industrial Science and Technology (AIST). He also serves as Chairperson, The System Device Roadmap Committee of Japan (SDRJ), Japan Society of Applied Physics (JSAP) and a Japan Representative of International Roadmap for Systems and Devices (IRDS), IEEE as the duty position of a Visiting Professor, Faculty of Science and Technology, Keio University. He worked in Central Research Laboratory, NEC (1987-2010), and Renesas Electronics Corporation (2010-2019) in the field of the advanced VLSI device and interconnect technologies including some budding stage developments on the “thinning & stacking” 3D integration and the oxide-FET integration in BEOL.
14:35 - 15:15 The Evolution of HPC and AI and Their Demands on FET Technologies : Masaaki Kondo (Keio Univ.): Abstract:
The evolution of high-performance computing (HPC) and artificial intelligence (AI) has co-evolved with advancements in cutting-edge semiconductor technologies, particularly those based on field-effect transistors (FETs). Continuous innovation in semiconductor technology has been the driving force behind the progress of HPC and AI. Today, the computational demands of HPC and AI are growing rapidly, and accordingly, the requirements for semiconductor technologies are becoming increasingly sophisticated and diverse. In particular, the rapid proliferation of generative AI has brought critical challenges in power consumption at data centers, necessitating significant improvements in energy efficiency. This presentation provides an overview of HPC and AI workloads and discusses the semiconductor requirements needed to support them from a system architecture perspective.

Biography

Masaaki Kondo received his Ph.D. from The University of Tokyo in 2003. He is currently a professor in the Department of Information and Computer Science at Keio University. He also serves as the division director of the Next-Generation HPC Infrastructure Development Division at the RIKEN Center for Computational Science, leading the research and development project of the next-generation Japanese national flagship supercomputer. His research interests include computer architecture, high performance computing, VLSI designs, artificial intelligence, and quantum computing.
15:15 - 15:30 Break
15:30 - 16:10 GAA: Genuine Architecture for AI Generation : Yuri Masuoka (Samsung): Abstract:
Throughout the long history of "the 100 Years of the FET" (FET100), various innovations in process, materials, and equipment led the tremendous success of the semiconductor industry. Looking back at past few decades, the major game changer has been the structural/dimensional changes which introduced new levels of collaborations with designers and vendors. At this turning point of the new century of FET100, Gate-All-Around (GAA) is poised to provide another technology leap for various applications. In this presentation, we will discuss the benefits that GAA can bring from the intrinsic transistor to the product level. GAA has already entered mass-production to start a new era, and further technology expansion with GAA is expected to continue our road into the AI generation.

Biography

Dr. Yuri Masuoka is Samsung Fellow in Foundry business unit of Samsung Electronics. She received Ph.D. degree in EE from The University of Tokyo. In 2000, she joined NEC corp., where she was engaged in an advanced low-power transistor technology development with high-k gate dielectric/body-biasing scheme.
From 2005 to 2006, she was a visiting industrial fellow at University of California at Berkeley, US, where she did research on 1/f noise characteristics of high-k gate dielectric transistor. Since 2006, she joined TSMC, Taiwan, where she developed the first foundry High-k/Metal-gate 28nm high performance device/process. In 2010, she joined Samsung Electronics Co., Ltd., Korea, where she has been working as Device leader to develop all advanced FinFET and GAA Platform technology from 14nm to 2nm, including extended application specific technology. She is currently served as an executive committee member of Symposium on VLSI Technology and Circuits.
16:10 - 16:50 Emerging FETs in Future Chiplet LSIs : Hitoshi Wakabayashi (Institute of Science Tokyo): Abstract:
Emerging FETs in future chiplet LSIs are going to be discussed firstly with the performance benchmarks including the complementary FET (CFET) or 3D-stacked FET (3DSFET), as compared to variable effective width (Weff) FETs such as the FinFETs and gate-all-around nanosheet (GAA-NS) FETs. However, since the power density values of such 3D-FETs are seriously needed to be concerned, the energy-delay products need to be reduced by high-mobility atomically-thin channel with short-channel-effect immunity, for which low-dimensional channels such as a transition-metal di-chalcogenide (TMDC) of MoS2, WS2, WSe2, ZrS2 etc. and carbon-nanotube (CNT) have been intensively investigated. Even having small energy-delay products, high heat dissipation technologies are required to be achieved mainly through the interconnects of both front- and back-side interconnects. Ultimately, 3D-fabric integrated circuits (ICs) having heat-dissipation-path networks in both vertical and horizontal directions are needed to be introduced as a future cubic-based IC rather than current cell-based IC. The future chiplet LSIs with such emerging FETs in tiny-sized huge systems must help to understand each other and cultivate the rational trust among the people in the World.

Biography

Hitoshi Wakabayashi is with Integrated Green-niX+ Research Unit, Institute of Integrated Research (IIR), Institute of Science Tokyo (Science Tokyo). He has joined the Tokyo Institute of Technology (Tokyo Tech, now Science Tokyo) since 2013 after NEC Corp., MIT and Sony Corp.
He also serves as the Research Supervisor of JST-PRESTO on Information Carriers and Their Integrated Materials/Devices/Systems, the Deputy Leader of Device Technology Division, Leading-edge Semiconductor Technology Center (LSTC), and Associate Member of Science Council of Japan. He had served as the Director of Research Institute for the Earth Inclusive Sensing (2018-2022) and the Member of the Education and Research Council (2022-2023) in Tokyo Tech. He had also engaged in the Research Representative at JST-CREST, the Directors of JSAP (2019-2020), JIEP (2019-2020) and Japan MOT Society since 2019. He had served as the Chairs in Symposium on VLSI Technology 2013, IEEE/EDTM 2018, IEEE/IWJT (2017/2019/2021/2023), IEEE EDS VLSI Technology & Circuits Committee (2020-2022) and IIT 2024.
16:50 - 17:30 Evolution of Technology to 3D-Memory in DRAM, Flash, and Emerging Memories : Jaeduk Lee (Samsung): Abstract:
Scaling limitations of planar memory technology have led the evolution in technology to 3D-memory, which was commercialized in flash memory a decade ago. Further scaling has been achieved to add more mold stacks in 3D-flash memory. However, the scaling has been realized in z-direction only, which makes the number of tiers increase exponentially. Thus, we have encountered other obstacles, such as mechanical failure, increased process cost, limitation in HARC (high-aspect ratio contact hole) etching. To overcome these obstacles, the 3D-memory has been developed to adopt COP (Cell over Peripheral circuits), and then recently, to Bonding-V NAND architecture. With these technologies at hand, it is time to incorporate 3D-memory technology into DRAM, which suffers from similar technology barriers. Candidates of 3D-DRAM architecture that enable it to integrate cells in 4F2 are under research and development. Thus, it is possible to extend the DRAM technology in the z-direction. In this talk, we will give a summary of the technology history of DRAM and Flash memories, along with prospects of the technology in near future including emerging memories. Technological barriers in 3D-memory will be introduced as well, especially in 3D-flash memory.

Biography

Jaeduk Lee received the M.S. and the Ph. D. degrees in electrical engineering from Koread Advanced Institute of Science and Technology, Taejon, Korea, in 1994 and 1999, respectively. In 1999, he joined Samsung Electronics, Yongin, Korea, where he is currently working on the 3D-NAND flash memory as a Master (Vice President) in Samsung. His research interests include the cell transistor of flash memory, peripheral transistors, and 3D-NAND cell architecture.
17:30 - 18:10 Progress and Future Challenges of Si and Wide Bandgap Semiconductor Power FETs : Tsunenobu Kimoto (Kyoto Univ.): Abstract:
Power semiconductor devices handle significant voltage (50–8,000 V) and current (1–1,000 A), being essential for meeting the exponential growth in power demand and for achieving efficient energy conversion, transfer, and storage. So far, Si-based power MOSFETs and IGBTs have been adopted for low-voltage and high-voltage applications, respectively. Si power devices have made remarkable strides, owing to the advanced simulation and process technologies. Si power MOSFETs outperform the so-called “Si limit” by using “super-junction” structures. In this application field, lateral AlGaN/GaN HEMTs on Si have emerged, demonstrating extremely low on-resistance and fast switching. AlGaN/GaN HEMTs, however, suffer from their low threshold voltage and lack of stable avalanche capability. In high-voltage applications, vertical SiC power MOSFETs exhibit a high potential and have been competing with Si IGBTs. Although SiC MOSFETs have significantly been penetrating into the market including EVs and railcars, the poor quality of MOS interface is still a major performance-limiting factor. In basic research, vertical GaN MOSFETs and Ga2O3 FETs have also been investigated. In this talk, the device structures, features, progress, and future challenges of Si and wide bandgap semiconductors are reviewed.

Biography

Tsunenobu Kimoto received the Ph.D. degree from Kyoto University in 1996 based on his work on SiC epitaxial growth, material characterization, and high-voltage diodes. From 1996 to 1997, he was a visiting scientist at Linköping University, Sweden. He is currently a Professor at Kyoto University.
His main research activity has been SiC electronics including SiC power devices, high-temperature devices, metal-oxide-semiconductor physics, ion implantation, optical and electrical characterization, point and extended defects, and epitaxial growth. He is currently serving as the President of the Japan Society of Applied Physics. He has published more than 600 papers in international journals and more than 650 papers (> 200 plenary/invited presentations) at international conferences. He received the Akasaki Isamu Award in 2022 and the IEEE Andrew S. Grove Award in 2024.
18:10 - 18:15 Closing Remark : Tsunenobu Kimoto (President, JSAP): Abstract:
This Special Workshop “FET100” provides the community with a historical background, current status, and future prospects of various kinds of Si and compound semiconductor FETs, creating an essential archive of the core semiconductor technology. It is my great pleasure that IEEE and JSAP (Japan Society of Applied Physics) celebrate the 100th anniversary of FETs and to jointly host this workshop as a commemorative event. I sincerely hope that continuous progress of FETs will trigger the next revolution of human society, leading to enrichment of daily life.

Biography

Tsunenobu Kimoto received the Ph.D. degree from Kyoto University in 1996 based on his work on SiC epitaxial growth, material characterization, and high-voltage diodes. From 1996 to 1997, he was a visiting scientist at Linköping University, Sweden. He is currently a Professor at Kyoto University.
His main research activity has been SiC electronics including SiC power devices, high-temperature devices, metal-oxide-semiconductor physics, ion implantation, optical and electrical characterization, point and extended defects, and epitaxial growth. He is currently serving as the President of the Japan Society of Applied Physics. He has published more than 600 papers in international journals and more than 650 papers (> 200 plenary/invited presentations) at international conferences. He received the Akasaki Isamu Award in 2022 and the IEEE Andrew S. Grove Award in 2024.

Special Workshop

Centennial Anniversary of FET Invention: Past, Present, and Future