Short Course 2

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Future Directions in Highspeed Wireline/Optical IO [Suzaku I+II]

Organizers: K. Yoshioka, Keio Univ.
Organizers: C. Tokunaga, Intel Corp.

Date & Time: Monday, June 12, 8:25A.M.-5:00P.M.

ChairpersonsT. Iizuka, The University of Tokyo
Chairpersons: N. Kocaman, Broadcom Ltd, Inc.

8:25 Introduction
8:30 Industry Megatrends Driving Connectivity R&D, T. C. Carusone, Univ. of Tronto / Alphawave Semi

Progress in computation and communication is increasingly bottlenecked by integrated circuit I/O. Industry megatrends are increasing connectivity demands overall, and spawning new, increasingly critical applications for die-to-die and optical links.  Die-to-die links demand the ultra low power and area, while our highest-speed interfaces now incorporate full-fledged digital modems operating over 100 Gbps.   This presentation provides an overview of this diverse technology landscape and the emerging solutions in each sector, providing a foundation for the talks that follow.

9:20 SerDes System Design and Implementation, T. Toifl, Cisco

This talk intends to give an overview of system design options for next generation high-speed SerDes designs. Starting from system modelling, we will describe the relevant options to reduce BER at high data rates, such as advanced DFE, duobinary signaling, MLSE and FEC coding, and show examples of current implementations. We will then describe several routes to possibly enhance data rates in the future, such as multi-wire differential transmission, simultaneous bi-directional and discrete multi-tone signaling.

10:10 Break
10:40 Trends in Digital Coherent Technologies with DSP ASICs for Optical Communication Systems, F. Hamaoka, NTT Corp.

To cope with the rapid growth in communication traffic, the capacity of optical transmission systems has continued to increase, as helped along by breakthroughs such as wavelength-division multiplexing and digital coherent technologies fully utilizing the capability of light waves by powerful digital signal processing (DSP). Digital coherent technologies with DSP application-specific integrated circuits (ASICs) support multi-rate and multi-modulation formats to meet the demands of multiple applications including long-haul, metro, and short-reach networks. Recently, a cutting-edge DSP for supporting up to 1.2 Tbps/carrier for digital coherent systems has been announced. This short course provides an overview of the trends in digital coherent technologies with DSP ASICs. It also presents our recent research and development pertaining to high-speed and high-capacity transmission utilizing digital coherent technologies.

11:30 Silicon Photonics Transceiver for High-Density Optical Interconnection, T. Nakamura, AIO Core

Silicon photonics technology is that it provides compact and low-cost photonics integrated circuits using strong optical confinement by silicon core and Si CMOS technology. In recent years, the growth of CPU/GPU performance has reached a ceiling due to the limit of gate miniaturization, and one of the ways to further increase computing power, especially for AI, is to connect many CPUs/GPUs and perform parallel distributed processing. For achieving those, low latency connections using high-speed, large-capacity optical interconnection are required. In this presentation, we will introduce compact, low-power, large-capacity optical interconnection transceivers from various companies that have been realized using silicon photonics technology. In addition, we will introduce the application of the high-temperature, highly reliable optical I/O core, that we have developed, to FPGA accelerators, PCIe, 5G antennas, and future automotive applications.

12:20 Lunch
13:10 Beyond the Interconnect, a Survey of Challenges on the Way to Enabling Heterogenous Chiplets in Package,
A. Kashem, Advanced Micro Devices, Inc. (AMD)

As we further race to bring together heterogenous compute and acceleration from the motherboard to the package, our industry will need to solve several new challenges. UCIe is a great step forward to address the interconnect aspect, but what else do we need? What standard form factors should we define? How do we enable debug/test beyond KGD? What kind of power delivery and thermal controls will we need? Can we also enable DVFS and binning? How do these challenges differ between advanced and organic packaging solutions? In this course, we will take a look at these questions and discuss some possible ways forward to address these challenges.

14:00 Architecture and Circuit Design of High-Speed Wireline Receivers, A. Balankutty, Intel Corp.

This short course will cover SerDes receiver design from first principles. We will review signal and noise budgeting for wireline systems, review ADC based receiver architectures for high-loss electrical links, design of analog front-end circuits and advanced equalization techniques for 100+Gb/s links.

14:50 Break
15:10 Design Considerations for High-Speed Transmitters in Wireline and Optical Communications, A. Vasani, Broadcom Ltd.

With the Data Bandwidth need increasing exponentially with AI/ML application, there is significant pressure on the analog front end circuits to lower the power while achieving high bandwidth for both wireline as well as optical links. The port speeds are quickly moving towards 200G/lane and the TX is an important part of enabling the link quality and is also important in determining the efficiency and area improvements from one generation to another. This talk gives a general overview of various design blocks involved in the design of a TX; including Clocking, Muxing and Driver/DAC. It will also talk about the key performance metrics and how they fit into the link closure.

16:00 Recent Developments and Challenges for NAND Flash Memory Interface, T. Toi, KIOXIA Corp.

The explosive increase in data used by machine learning applications and big data analysis is requiring high-bandwidth and large-capacity storage systems using NAND flash memories. Increased capacity of NAND flash memory has been driven by technologies for 3D architecture of memory cells and higher-level cells, while higher bandwidth of NAND flash memory interfaces, e.g., Toggle DDR and ONFi, has been realized by several techniques such as double data rate transfer, on-die termination and various calibrations. However, NAND flash memory interfaces have inherent challenges, and that makes it difficult to follow the high speed trends of host interfaces, e.g., PCIe and CXL, connecting a host CPU and a controller of a storage. Recently proposed topologies using additional bridge chips, which could replace conventional multi-drop bus topology of NAND flash memory interfaces, are expected to realize both high-bandwidth and large-capacity.
In this talk, the basic configuration and existing techniques of NAND flash memory interfaces will be introduced while discussing the differences against DRAM interfaces, leading in terms of transfer rate. Then, we will elaborate on latest published techniques to address challenges of NAND flash memory interfaces.