Short Course 1

* If you encounter menus do not work upon clicking, delete your browser's cache.

Advanced CMOS Technologies for 1 nm & Beyond

Chairpersons: K. Tomida, Rapidus Corp.
Chairpersons: Y. Liang, NVIDIA Corp.

Date & Time: Monday, June 12, 8:25A.M.-5:00P.M.

8:25 Introduction
8:30 Advanced CMOS Transistor Scaling towards 1nm Node and Beyond, Chung-Hsun Lin, Intel Corp.

As FinFET scaling comes to an end in 3nm node, there are several innovative device and standard cell architectures considered for 2nm node and beyond: from gate-all-around (GAA) transistor, backside power delivery, complementary FET (CFET), to atomic channel FET with 2D materials. The GAA transistor is the most pragmatic architecture in the near term to enable incremental contact-poly pitch and gate length scaling because of its limited perturbation to a conventional FinFET process integration and design flows. Backside power delivery and CFET (3D stacking) technology brings additional cell level area scaling benefit as well as heterogeneous integration benefit for high mobility channel enablement.  2D material FET provides the ultimate gate length scaling with high mobility channel capability. In this short course, we will focus on technology and device design value proposition for these innovations with the corresponding engineering opportunities and challenges for high volume manufacturing.

9:20 Advances in EUV Lithography: From 0.33NA Technology towards High-NA and Beyond, E. van Setten, ASML

DUV lithography has been the workhorse for the industry for the past decades. Multiple customers have now entered the high volume manufacturing phase with EUV lithography using ASMLs NXE scanners. To enable further cost-effective scaling, ASML and Zeiss developed the next generation High-NA EUV platform with an NA of 0.55, that builds on the EUV technology developed on the 0.33NA platform.
In this short course we will give an overview of the current status of 0.33NA EUV technology and the next generation High-NA EUV platform, including a historic perspective. We illustrate how the learnings from the past are being applied and what new technologies are being developed to drive the EUV lithography roadmap. We will cover advances in scanner development, such as source and optics, but also developments in the eco-system, like mask, photoresist and OPC. We conclude with an outlook of what may come after High-NA EUV.

10:10 Break
10:40 Advanced Logic Transistor Process Technology towards 1-nm Node, N. Yoshida, Applied Materials, Inc.

After several generations of FinFET scaling to the latest 3-nm node [1], advanced logic transistor architecture continues to evolve to horizontal gate-all-around (GAA) FET with vertically stacked Si nano-sheet (NS) channel [2, 3]. Multiple innovations of process technology are required for NS-GAA implementation in high volume manufacturing. Beyond NS-GAA and other scaling boosters such as backside power delivery, novel transistor architectures are in the pipeline for future CMOS scaling. One of the proposed new architectures is to vertically stack PMOS and NMOS, also known as CFET, for effective CMOS area scaling. CFET fabrication is proposed in mainly two different integration approaches, sequential and monolithic integration [4 - 6]. 
This short course describes process challenges and process technology solutions for GAAFETs as the next transistor inflection. In addition, we’ll discuss CFET process integration approaches and key technology innovations.

11:30 Challenges and Innovations for Advanced BEOL Scaling at the 1nm Node and Beyond, C. Penny, IBM Corp.

For over twenty years, dual damascene copper interconnects have been the industry standard for advanced logic technologies. In this time, a continuous series of innovations has enabled scaling of the interconnect by a factor of 10. In recent years, however, the rate of scaling has slowed, and new advances will be needed to continue extending Moore’s Law. In this talk, I will discuss recent advances in interconnect research and the challenges that remain to continue scaling. Several recent innovations which enable the extension of the copper damascene integration scheme will be reviewed. I will also look at the options for scaling beyond copper damascene. Subtractive ruthenium has emerged as one of the most likely technologies to scale beyond copper. I will review the potential advantages of alternate metals, including ruthenium, as well as the challenges and advances that will enable scaling to the 1nm node and beyond.

12:20 Lunch
13:10 CMOS Scaling by Backside Power Delivery, N. Horiguchi, imec

Current CMOS chips have both signal routing and power delivery in frontside of wafer. However, frontside power delivery has to go through multiple metal layers and wide power metal lines consume area, which cause IR drop and routing congestions, respectively. It is an attractive option to separate signal routing in frontside and power delivery in backside. It improves routing congestions and IR drop. Several backside power delivery options are proposed, and they have trade-offs in terms of process complexity, area scaling and IR drop. Backside power delivery integration requires extreme wafer thinning and metal connection from backside, which could cause challenges in integration control, such as wafer distortion and litho alignment, and device performance, such as channel stress and self-heating. Backside power delivery concept could be extended to functional backside, such as backside global interconnect and backside device, which enables further CMOS scaling by using backside engineering.

14:00 Process Control Solutions for the Era of 3D Architecture Devices, S. H. Han, Nova

As semiconductor devices continue to scale, the performance limitations of 2D architectures are driving the migration to 3D architectures. But in doing so, new challenges arise for process control solutions to detect potential variations in structure and in materials to maintain high quality processes for targeting performances.
This course will describe the latest metrology technologies and challenges in serving 3D device processes, teach participants how the shift from 2D to 3D architecture devices are resulting in new performance requirements for process control solutions, and cover principles of metrology concepts including the optical, X-ray, E-beam and scanning probe microscopy. This course will also teach the lab solution for in-line solutions for 3D process control analysis and cover new trends in problem solving in the metrology industry to address challenges for 3D devices, including machine learning techniques and hybrid metrology systems at high volume manufacturing.

14:50 Break
15:10 Semiconductor Packaging Revolution in the Era of Chiplets, Y. Orii, Rapidus Corp.

Since the semiconductor cost for state-of-the-art nodes is increasing, "Chiplet" technology is in the spotlight as a new evolutionary path to scale up integration and improve performance and reduce the total cost. With an SoC, a chip might incorporate a CPU, plus an additional several IP blocks on the same chip. That design is then scaled by the advanced node, which is an expensive process. With a chiplet model, those several IP blocks are hardened into smaller dies(chiplets) and those dies are integrated on an interposer to build a system. Those chips must be connected in the shortest length while considering signal integrity and power integrity so that the cutting-edge packaging technology is the key to improve the performance of IT equipments. In this short course, the advanced 2.1D, 2.3D, 2.5D and 3D packaging technologies will be introduced as well as the several interposer technologies.

16:00 Device Technology for 2D Layered Semiconductor FETs: Challenge & Perspective, K. Nagashio, The Univ. of Tokyo

Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. The circuits consisting of more than 50k transistors have been demonstrated, including inverters, ring oscillators, and static random access memory cells. Moreover, the successful integration of monolayer MoS2 nanosheet FET in a gate-all-around configuration has been demonstrated last year. While steady progress has been made on 2D integration technology, some bottlenecks are still present. In this short course, the present status and the perspective on the 2D electronics will be discussed.