Short Course 1
Key VLSI technologies in the AI era
Chairpersons: Shosuke Fujii, KIOXIA Corp.
Chairpersons: Anabela Veloso, Imec
Date & Time: Monday, June 9, 8:25A.M.-4:35P.M.
- 8:25 Opening
- 8:30 CMOS Scaling Exploration: Technology Trends and System-Level Perspectives, Lucy Yang, TSMC
-
Abstract:
Over the past five decades, CMOS scaling has been a primary driver of the electronics industry and has provided a path toward denser, faster, more efficient and cost-effective technologies. Multiple waves of innovations in materials and transistor architectures have emerged from both industry and academia to overcome the challenges of scaling. This short course will explore the elements of logic scaling covering dimensional scaling components of standard cell and key power-performance factors for extremely scaled devices. Physics and key process technology enablers will be discussed. Complementary FET (CFET), which consists of stacked transistors, is a promising architecture for enabling continuous logic density scaling. Other scaling-related factors that impact circuit design, such as local layout effects and process variability, will be highlighted. With fewer scaling boosters left at cell level, the system-technology co-optimization (STCO)-oriented approach becomes increasingly important. Advanced packaging, enabling heterogeneous integration of chiplets optimized for different functions, offers a path to the continuation of Moore's law. - 9:20 2D materials and their application space - Recent insights gained -, Joerg Appenzeller, Purdue Univ.
-
Abstract:
After introducing two-dimensional (2D) materials for advanced logic applications, my talk will discuss in detail experimental progress towards high performance n-type and p-type field-effect transistors (FETs) from two different transition metal dichalcogenides (TMDs). Next, I will discuss how one and the same TMD, i.e. MoTe2, can be processed to enable n-type or p-type behavior at will, allowing to build an integrated inverter. Individual device and inverter characteristics will be discussed and my group’s work will be put in the context of previously published data. Following these three sections on transistors, I will discuss three recent discoveries that are benefitting from 2D materials. I will first present results on template contacts to layered 2D materials. This will be followed by a discussion of a novel RRAM cell from multi-layer MoTe2 and MoxW1-xTe2 that allows for a field-induced phase transition between a low and a high resistive state. Last, to conclude my presentation, I will demonstrate the most compact 1T TCAM cell that has been built employing a multi-layer TMD transistor with graphene source/drain contacts. - 10:10 Break
- 10:25 Heterogenous System Partitioning, the 2.5D and 3D integration landscape and roadmap, Eric Beyne, imec
-
Abstract:
Monolithic CMOS scaling is by itself unable to keep-up with system scaling requirements. Heterogeneous 2.5D and 3D integration technologies are increasingly used to complement the system scaling requirements. This has let to a proliferation of advanced packaging and interconnection technology flavors, all with their own names and acronyms and roadmaps. To find our way in this forest of technologies we need to organize these technologies and use correct benchmarks to compare technologies and identify the proper application spaces for each one of them.
In this SC we explore the relationship between the system level design hierarchy, the system partitioning level and the required 2.5D or 3D interconnect density requirements. This helps in ordering the 3D technology landscape based on their 3D interconnect capability. This 3D interconnect landscape is however not static, each technology option has its own roadmap, resulting in a shifting 3D landscape over time. The presentations will address the key 3D technologies and their respective roadmaps, include 2.5D Si and RDL based interposer technology, solder µbump and Cu-Cu (hybrid) bonding die-to-wafer bonding; wafer-to-wafer hybrid bonding technologies, TSV scaling down to standard cell dimensions, leading to standard-cell and even transistor-level backside connectivity. This will allow future systems concepts integrating multiple density integrated device layers, interlaced with dense BEOL interconnect layers, the CMOS2.0 stacking concept.
- 11:25 Etch and material innovations for advanced logic and memory technologies, Thorsten Lill, Lam Research
-
Abstract:
Monolithic 3D integration is one of the vectors advancing device density of logic and memory integrated circuits. We will analyze device road maps and identify salient device architectures and materials. Key patterning innovation areas are identified. The ability to etch features with ever increasing high aspect ratios enables device cost roadmaps. Selective isotropic etching in combination with atomic layer deposition allows the formation of laterally stacked devices. New etching technologies are needed to pattern novel materials. To meet these requirements, innovative etching technologies such as cryogenic, thermal and atomic layer etching are being introduced to the industry. We will introduce the fundamentals, existing and potential applications as well as the capabilities and limits of these advanced these etching technologies. The goal of this short course is to inform 3D device design technology co-optimization efforts. - 12:05 Lunch
- 12:55 DRAM history and challenges, Yoshihiro Matsumoto, Micron
-
Abstract:
Dynamic Random Access Memory (DRAM) technology continues to evolve, driven by the need for higher density, better performance, and lower power consumption such as High Bandwidth Memory (HBM), Processor-In-Memory (PIM) and Low Power Wide IO (LPW) those are led by AI technology. This presentation delves into the current state of DRAM technology, focusing on the 6F² cell structure, which is pivotal for achieving high-density memory. We will explore the challenges associated with scaling, particularly the difficulties in maintaining cell capacitance, which is crucial for DRAM refresh performance and row hammer immunity.
As DRAM access device scales down, word line scaling faces significant hurdles, impacting overall performance. Additionally, achieving reasonable contact resistance for digit lines and cell contacts becomes increasingly difficult. To address these challenges, Error Correction Code (ECC) technology emerges as a breakthrough, offering potential solutions for enhancing DRAM scaling. This presentation navigates through the intricacies of DRAM technology, highlighting the innovations and obstacles that shape its future. - 13:45 Current landscape and future outlook of emerging memory technologies, Soo Gil Kim, SK hynix
-
Abstract:
The advancement of emerging memory technologies, including PCM, ReRAM, STT-MRAM, and Ferroelectric memory, has been propelled by various R&D activities spanning materials, processes, device innovations, and circuit design. During a period marked by surging interest in these novel memories, research efforts concentrated on developing high-capacity solutions with the potential to supplant DRAM and NAND. However, despite the intense technological momentum, these efforts initially fell short of cultivating a technology capable of capturing a substantial market share.
With the shift in computing paradigms and environments, R&D and commercialization efforts have diversified to encompass standalone, embedded, and AI-driven devices, all aiming to tap into emerging application areas. As the computing landscape rapidly evolves—with increasing emphasis on memory-centric and AI computing solutions that fulfill high-performance and low-power demands—a variety of innovative technologies are being proposed to transcend the limitations of conventional memories and processors. The performance of next-generation memory, including emerging memories, varies according to specific applications, necessitating technologies that either segment or integrate IC components. Consequently, these technical considerations should be incorporated into the developmental strategies and objectives of emerging memory technologies.
This presentation provides an overview of the current landscape and future outlook of emerging memory technologies, set against the backdrop of rapidly evolving trends in memory semiconductors. - 14:35 Break
- 14:50 DTCO/STCO for Multi-objective Optimization from Device to System, Hyung-Ock Kim, Samsung
-
Abstract:
The importance of Design Technology Co-Optimization has ever been increased. It contributes large portion of benefit for power, performance, and area beyond intrinsic scaling limitation. However, power, performance, and area could be trade off for each other depending on choice during DTCO. Besides, we should consider device, BEOL, standard library, block design, and EDA together for seamless implementation. This course will introduce DTCO in point of multi-objective optimization problem in nano-scale technologies. - 15:40 Heterogeneous Integration Technologies for 3D Integrated CMOS Image Sensors, Yoshihisa Kagawa, Sony
-
Abstract:
In the field of CMOS Image Sensor (CIS), there has been high demand for new functions that can respond to various photo taking scenes. To meet the market needs, we have started the mass production of Back Illuminated CIS (BI CIS) and stacked BI CIS respectively. Those CISs have effectively improved the sensitivity and functionality compared with the conventional Front Illuminated CIS. To fabricate high performance and highly productive stacked BI CISs, we have developed a novel 3D stacking technology called Cu Cu hybrid bonding. The fine pitch Cu Cu hybrid bonding has achieved the wide dynamic range and high speed processing. Thus, our 3D stacking technologies have successfully evolved the CISs from viewpoint of performance improvement, performance expansion and functional expansion. In the very near future, our cutting edge devices will be key not only for mobile gadgets, surveillance, factory automation, autonomous driving, medical imaging but also for robotics and AI system. This short course aims to provide a comprehensive overview of the Heterogeneous Integration technologies for 3D Integrated CISs. It will also discuss upcoming 3D stacking process technologies for the next generation CISs. - 16:30 Closing