Welcome to the 2000 Symposium on VLSI Technology

 

Welcome to the 2000 Symposium on VLSI Technology. On behalf of the organizing committees, we invite you to attend the 2000 Symposium on VLSI Technology to be held from June 12-15 in Honolulu, Hawaii.

In addition to being in a new millennium, the 2000 Symposium represents the 20th anniversary of the Symposium on VLSI Technology. We on the technical program committees believe we have assembled an exciting and informative program. More than 250 excellent papers were submitted from all over the world, representing a record number of submissions, and indicating the continued growth of the Symposium. From among this excellent work, we have selected 84 contributed papers organized into 21 sessions. In addition, we have two distinguished industry representatives to speak at the plenary session. Dr. Youssef El-Mansy, Vice President, Technology and Manufacturing Group, and Director of Logic Technology Development at Intel Corporation, will speak on "The VLSI Symposium and Silicon Technology – A Twenty Year Perspective", and Dr. Masao Fukuma of NEC Corporation will speak on "New Frontiers of Sub-100nm VLSI Technology – Moving Toward Device and Circuit Co-Design".

Four Rump Sessions are planned for the evening of June 14th as a means to facilitate informal discussions among researchers. A Joint Rump Session with the Symposium on VLSI Circuits will address "Circuit and System Technology in the Year 2010". The three other sessions will cover specific technology related topics of timely interest:

  1. DRAM scaling challenges and Innovations between now and 2010: How far can the DRAM cell shrink?
  2. Lithography for sub-100nm, optical vs. non-optical.
  3. Novel structures and processes for continued MOSFET scaling: What, when, and whether?

A one-day Short Course, planned for Monday June 12, will cover, "Key Process Technologies for 130-100nm Generations". This should be an excellent opportunity for experienced as well as new engineers to broaden their technical base.

The Symposium registration fee covers all of the sessions including the Rump Sessions. Coffee breaks and the banquet are also included. Registration for the Short Course is extra. The detailed registration fees and hotel reservation schedules are included in the Advance Program.

As in past years, we expect a strong participation from leaders of the VLSI industry and academic researchers. We look forward to an exciting Symposium in Honolulu. Please join us.

Craig Lage

Tadashi Nishimura

Program Chairman

Program Co-Chairman


2000 Symposium on VLSI Technology
Advance Program

 

SESSION 1 - Tapa I/II/III

Plenary Session

Tuesday, June 13, 8:30 a.m.

Chairpersons:

Craig Lage, Motorola, Inc.
Tadashi Nishimura, Mitsubishi Electric

8:30 a.m.

Welcome and Opening Remarks

 

Antonio Alvarez, Cypress Semiconductor
Eiji Takeda, Hitachi

8:45 a.m.

VLSI Symposium and Silicon Technology: A Twenty Year Perspective

1.1

Youssef El-Mansy, Intel Corp.

9:25 a.m.

New Frontiers of Sub-100nm VLSI Technology – Moving Toward Device and Circuit Co-Design,

1.2

Masao Fukuma, NEC Corp.

 

SESSION 2 - Tapa I

Highlights

Tuesday, June 13, 10:20 a.m.

Chairpersons:

R. De Keersmaecker, IMEC,
T. Kunio, NEC Corp.

10:20 a.m.

A 0.13[ m DRAM Technology for Giga bit Density Stand-alone and Embedded DRAMs,

2.1

K.N. Kim, T.Y. Chung, H.S. Jeong, J.T. Moon, Y.W. Park, G.T. Jeong, K.H. Lee, G.H. Koh, D.W. Shin, Y.S. Hwang, D.W. Kwak, H.S. Uh, D.W. Ha, J.W. Lee, S.H. Shin, M.H. Lee, Y.S. Chun, J.K. Lee, B.J. Park, J.H. Oh, J.G. Lee, S.H. Lee, Samsung Electronics Company, Ltd., Kyungki-Do, Korea

10:45 a.m.

A Modular 0.13[m Bulk CMOS Technology for High Performance and Low Power Applications,

2.2

L. Han, S. Biesemans, J. Heidenreich, K. Houlihan, C. Lin*, V. McGahay, T. Schiml*, A. Schmidt*, U. Schroeder*, M. Stetter*, C. Wann, D. Warner*, R. Mahnkopf* and B. Chen, IBM, Hopewell Junction, NY and *Infineon Technologies Corp., Hopewell Junction, NY

11:10 a.m.

A 70 nm Gate Length CMOS Technology with 1.0 V Operation,

2.3

A. Ono, K. Fukasaku, T. Matsuda, T. Fukai, N. Ikezawa, K. Imai, and T. Horiuchi, NEC Corporation, Kanagawa, Japan

11:35 a.m.

High Quality La2O3 and Al2O3 Gate Dielectrics with Equivalent Oxide Thickness 5-10 ,

2.4

A. Chin, Y.H. Wu, S.B. Chen, C.C. Liao, and W.J. Chen*, National Chiao Tung University, Hsinchu, Taiwan and *National Yun-Lin Poly-technic Institute, Huwei, Taiwan

12:00 p.m.

Lunch

 

SESSION 3 - Tapa I

Copper Interconnect

Tuesday, June 13, 1:30 p.m.

Chairpersons:

R. Havemann, TI/SEMATECH,
J. Ida, Oki Electric

1:30 p.m.

Highly Thermal-Stable, Plasma-Polymerized BCB Polymer Film (k=2.6) for Cu Dual-Damascene Interconnects,

3.1

J. Kawahara, K. Shiba, M. Tagami, M. Tada, S. Saito, T. Onodera, K. Kinoshita, M. Hiroi, A. Furuya, K. Kikuta and Y. Hayashi, NEC Corporation, Kanagawa, Japan

1:55 p.m.

A 0.20[m CMOS Technology with Copper-Filled Contact and Local Interconnect,

3.2

R. Islam, S. Venkatesan, M. Woo, R. Nagabushnam, D. Denning, K. Yu, O. Adetutu, J. Farkas, T. Stephens and T. Sparks, Motorola, Austin, TX

2:20 p.m.

Copper Distribution Behavior Near a SiO2/Si Interface by Low-Temperature (<400° C) Annealing and its Influence on Electrical characteristics of MOS-Capacitors,

3.3

K. Hozawa, T. Itoga, S. Isomae, J. Yugami and M. Ohkura, Hitachi, Ltd., Tokyo, Japan

2:45 p.m.

Copper Contamination Induced Degradation of MOSFET Characteristics and Reliability,

3.4

M. Inohara, H. Sakurai*, T. Yamaguchi, H. Tomita, T. Iijima, H. Oyamatsu, T. Nakayama, H. Yoshimura and Y. Toyoshima, Toshiba Corporation, Yokohama, Japan and *Toshiba Corporation, Kawasaki, Japan

3:10 p.m.

Break

 

SESSION 4 - Tapa III

Novel Devices

Tuesday, June 13, 1:30 p.m.

Chairpersons:

Y. Taur, IBM Research Center,
E. Suzuki, Electrotechnical Laboratory

1:30 p.m.

MISS Tunnel Diode: A Capacitorless 4F2 Memory Cell for Sub-0.1 [m Era,

4.1

H. Matsuoka, T. Sakata and S. Kimura, Hitachi, Ltd., Tokyo, Japan

1:55 p.m.

Mass-Productive High Performance 0.5[m Embedded FRAM Technology with Triple Layer Metal,

4.2

A. Itoh, Y. Hikosaka, T. Saito, H. Naganuma, H. Miyazawa, Y. Ozaki, Y. Kato, S. Mihara, H. Iwamoto, S. Mochizuki, M. Nakamura and T. Yamazaki, Fujitsu Limited, Kanegasaki, Japan

2:20 p.m.

A Novel 1T1C Capacitor Structure for High Density FRAM,

4.3

N.W. Jang, Y.J. Song, H.H. Kim, D.J. Jung, B.J. Koo, S.Y. Lee, S.H. Joo, K.M. Lee and K. Kim, Samsung Electronics Company, Ltd., Kyungki-Do, Korea

2:45 p.m.

SiGe Heterojunctions in Epitaxial Vertical Surrounding-Gate MOSFETs,

4.4

C.K. Date and J.D. Plummer, Stanford University, Stanford, CA

3:10 p.m.

Break

 

SESSION 5 - Tapa I

High-K Dielectrics

Tuesday, June 13, 3:25 p.m.

Chairpersons:

J. Lee, University of Texas,
S. Kawamura, Fujitsu Ltd.

3:25 p.m.

Performance of MOSFETs with Ultra Thin ZrO2 and Zr Silicate Gate Dielectrics,

5.1

W.-J. Qi, R. Nieh, B.H. Lee, K. Onishi, L. Kang, Y. Jeon, J. Lee, V. Kaushik*, B.-Y. Neuyen*, L. Prabhu*, K. Eisenbeiser* and J. Finder*, University of Texas, Austin, TX and *Motorola, Inc.

3:50 p.m.

Novel MIS Al2O3 Capacitor as a Prospective Technology for Gbit DRAMs,

5.2

I.S. Park, B.T. Lee, S.J. Choi, J.S. Im, S.H. Lee, K.Y. Park, J.W. Lee, Y.W. Hyung, Y.K. Kim, H.S. Park, Y.W. Park, S.I. Lee and M.Y. Lee, Samsung Electronics Co., Ltd., Kyoungki-Do, Korea

4:15 p.m.

Single-Layer Thin HfO2 Gate Dielectric with n+ -Poly-silicon Gate,

5.3

L. Kang, Y. Jeon, K. Onishi, B.H. Lee, W-J. Qi, R. Nieh, S. Gopalan and J.C. Lee, Univ. of Texas, Austin, TX

4:40 p.m.

Characteristics of AL2O3 Gate Dielectric Prepared by Atomic Layer Deposition for Giga Scale CMOS DRAM Devices,

5.4

D.-G. Park, H.-J. Cho, C. Lim, I.-S. Yeo, J.-S. Roh, C.-T. Kim, and J.-M. Hwang, Hyundai Electronics Industries Company, Ltd., Kyoungki-Do, Korea

 

SESSION 6 - Tapa II

Process Technology

Tuesday, June 13, 3:25 p.m.

Chairpersons:

W. Arnold, ASM Lithography,
J.-M. Hwang, Hyundai Microelectronics

3:25 p.m.

A Novel CVD Polymeric Anti-Reflective Coating (PARC) for DRAM, Flash and Logic Device with 0.1[m CoSi2 Gate,

6.1

K. Linliu, M.-R. Kuo, Y.-R. Huang, S.-C. Lin, S.-P. Jeng and C.-S. Chen, Worldwide Semiconductor Manufacturing Corp., Hsinchu, Taiwan

3:50 p.m.

Making 50nm Transistors with 248 nm Lithography,

6.2

P. Stolk, P. Dirksen, C. Juffermans, R. Roes, A. Montree, J. v. Wingerden, W. de Laat, W. Gehoel-v.Ansem, M. Kaiser, J. Kwinten and C. van der Poel, Philips Research, Eindhoven, The Netherlands

4:15 p.m.

EB Projection Lithography for 60-80nm ULSI Fabrication,

6.3

K. Tokunaga, F. Koba, M. Miyasaka, Y. Takaishi, K. Noda, H. Yamashita, K. Nakajima, and H. Nozue, NEC Corporation, Kanagawa, Japan

4:40 p.m.

A High Performance Drying Method Enabling Clustered Single Wafer Wet Cleaning,

6.4

P. Mertens, G. Doumen, J. Lauerhaas, K. Kenis, W. Fyen, M. Meuris, S. Arnauts, K. Devriendt, R. Vos and M. Heyns, IMEC, Leuven, Belgium


SESSION 7 - Tapa I

Embedded DRAM

Wednesday, June 14, 8:30 a.m.

Chairpersons:

R. Mahnkopf, Siemens Microelectronics,
T. Eimori, Mitsubishi Electric

8:30 a.m.

A Simple Embedded DRAM Process for 0.16-[m CMOS Technologies,

 7.1

C.T. Liu, P.W. Diodato, S. Rogers, W.Y.C. Lai, C.J. Chen, E.J. Lloyd, C.Y. Sun, D. Barr, R. Liu, C.P. Chang, L. Trimble, C.S. Pai and H. Vaidya, Lucent Technologies, Bell Laboratories, Murray Hill, NJ

8:55 a.m.

High Density Embedded DRAM Technology with 0.38[m Pitch in DRAM and 0.42[m Pitch in LOGIC by W/PolySi Gate and Cu Dual Damascene Metallization,

7.2

N. Takenaka, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, M. Inuishi*, T. Oashi*, K. Tsukamoto*, S. Komori*, K. Tomita*, T. Inbe*, A. Ohsaki*, T. Hanawa*, S. Sakamori*, M. Shirahata*, J. Tsuchimoto* and T. Eimori*, Matsushita Electronics Corporation, Kyoto, Japan and *Mitsubishi Electric Corp., Hyogo, Japan

9:20 a.m.

A 0.17[m Embedded DRAM Technology with 0.23[m2 Cell Size and Advanced CMOS Logic,

7.3

H. Wurzer, K. Feldner, W. Graf, G. Curello, J. Faul, D. Weber and A. Kieslich, Infineon Technologies Dresden, Dresden, Germany

9:45 a.m.

0.25 [m Merged Bulk DRAM and SOI Logic Using Patterned SOI,

7.4

R. Hannon, S.S.K. Iyer, D. Sadana, J. Rice, H. Ho, B. Khan and S.S. Iyer, IBM Microelectronics Division, Hopewell Junction, NY

10:10 a.m.

Break

 

SESSION 8 - Tapa II

Gate Electrode Engineering

Wednesday, June 14, 8:30 a.m.

Chairpersons:

C. Osburn, North Carolina State University,
K. Shibahara, Hiroshima University

8:30 a.m.

Damascene Metal Gate MOSFETs with Co Silicided Source/Drain and High-k Gate Dielectrics,

8.1

K. Matsuo, T. Saito, A. Yagishita, T. Iinuma, A. Murakoshi, K. Nakajima, S. Omoto and K. Suguro, Toshiba Corporation, Yokohama, Japan

8:55 a.m.

Dual-Metal Gate Technology for Deep-Submicron CMOS Transistors,

8.2

Q. Lu, Y.C. Yeo, P. Ranade, H. Takeuchi, T-J King, C. Hu, S.C. Song*, H.F. Luan* and D-L Kwong*, University of California, Berkeley, CA and *University of Texas, Austin, TX

9:20 a.m.

A Thin Amorphous Silicon Buffer Process for Suppression of W Polymetal Gate Depletion in PMOS,

8.3

F. Ohtake, Y. Akasaka*, A. Murakoshi*, K. Suguro* and T. Nakanishi, Fujitsu Laboratories Ltd. and *Toshiba Corp., Yokohama, Japan

9:45 a.m.

Deep Sub-100nm CMOS with Ultra Low Gate Sheet Resistance by NiSi,

8.4

Q. Xiang, C. Woo, E. Paton, J. Foster, B. Yu and M.-R. Lin, Advanced Micro Devices, Sunnyvale, CA

10:10 a.m.

Break

 

SESSION 9 - Tapa I

DRAM Cells

Wednesday, June 14, 10:25 a.m.

Chairpersons:

C. Dennison, Micron Technology,
H. Kuroda, Sony Corp.

10:25 a.m.

A 0.135 [m2 6F2 Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAM,

9.1

C. Radens, U. Gruening*, J. Mandelman, M. Seitz*, T. Dyer, D. Lea, D. Casarotto*, L. Clevenger, L. Nesbit, R. Malik*, S. Halle, S. Kudelka*, H. Tews*, R. Divakaruni, J. Sim, A. Strong, D. Tibbel, N. Arnold*, S. Bukofsky, J. Preuninger*, G. Kunkel* and G. Bronner, IBM Microelectronics, Hopewell Junction, NY and *Infineon Technologies, Hopewell Junction, NY

10:50 a.m.

Transistor on Capacitor (TOC) Cell with Quarter Pitch Layout for 0.13[m DRAMs and Beyond,

9.2

M. Sato, S. Ishibashi, T. Kajiyama, M. Sakuma, I. Mizushima, Y. Tsunashima, F. Shoji, H. Yano, A. Nitayama and T. Hamamoto, Toshiba Corporation, Yokohama, Japan

11:15 a.m.

Scaling Guideline of DRAM Memory Cells for Maintaining the Retention Time,

9.3

S. Ueno, Y. Inoue and M. Inuishi, Mitsubishi Electric Corporation, Hyogo, Japan

11:40 a.m.

Improvement of the Tail Component in Retention Time Distribution Using Buffered N-Implantation With Tilt and Rotation (BNITR) for 0.2 [m DRAM Cell and Beyond,

9.4

I. Kim, N. Kim, H. Jung, H. Kwon, S. Ok, J. Kim, P. Sim, J. Park, D. Park, and S. Jang, Hyundai Microelectronics Company, Ltd., Chungbuk, Korea

12:05 p.m.

Lunch

 

SESSION 10 - Tapa II

Gate Oxide Scaling and Reliability

Wednesday, June 14, 10:25 a.m.

Chairpersons:

C.S. Pai, Lucent Technologies, Bell Labs,
M. Ohkura, Hitachi

10:25 a.m.

Limits of Gate-Oxide Scaling in Nano-Transistors,

10.1

B. Yu, H. Wang, C. Riccobene, Q. Xiang and M.R. Lin, Advanced Micro Devices, Inc., Sunnyvale, CA

10:50 a.m.

NBTI Enhancement by Nitrogen Incorporation Into Ultrathin Gate Oxide for 0.10-[m Gate CMOS Generation,

10.2

N. Kimizuka, K. Yamaguchi, K. Imai, T. Iisuka, C.T. Liu*, R.C. Keller* and T. Horiuchi, NEC Corporation, Kanagawa, Japan and *Bell Laboratories, Lucent Technologies, Murray Hill, NJ

11:15 a.m.

Breakdown Measurements of Ultra-Thin SiO2 at Low Voltage,

10.3

J. Stathis, A. Vayshenker*, P. Varekamp*, E. Wu**, C. Montrose*, J. McKenna**, D. DiMaria, L.-K. Han*, E. Cartier, R. Wachnik* and B. Linder, IBM Research Division, Yorktown Heights, NY and *IBM Microelectronics Division, Hopewell Junction, NY and **IBM Microelectronics Division, Essex Junction, VT

11:40 a.m.

Quantitative Yield and Reliability Projection from Antenna Test Results - A Case Study,

10.4

P. Mason, K.P. Cheung*, D.K. Hwang, M. Creusen**, R. Degraeve** and B. Kaczer**, Bell Laboratories, Lucent Technologies, Orlando, FL and *Bell Laboratories, Lucent Technologies, Murray Hill, NJ and **IMEC, Leuven, Belgium

12:05 p.m.

Lunch

 

SESSION 11 - Tapa I

DRAM Capacitors

Wednesday, June 14, 1:30 p.m.

Chairpersons:

T. Seidel, Genus Corp.,
S.-I. Lee, Samsung Electronics

1:30 p.m.

Development of CVD-Ru/Ta2O5/CVD-TiN Capacitor for Multigigabit-Scale DRAM Generation,

11.1

W.D. Kim, J.W. Kim, S.J. Won, S.D. Nam, B.Y. Nam, C.Y. Yoo, Y.W. Park, S.I. Lee and M.Y. Lee, Samsung Electronics Company, Ltd., Kyungki-Do, Korea

1:55 p.m.

A Conformal Ruthenium Electrode for MIM Capacitors in Gbit DRAMs Using the CVD Technology Based on Oxygen-Controlled Surface Reaction,

11.2

M. Hiratani, T. Nabatame, Y. Matsui, Y. Shimamoto, Y. Sasago, Y. Nakamura, Y. Ohji, I. Asano and S. Kimura, Hitachi, Ltd., Japan

2:20 p.m.

Low Temperature (<500 ° C) SrTiO3 Capacitor Process Technology for Embedded DRAM,

11.3

J. Nakahira, M. Kiyotoshi*, S. Yamazaki*, M. Nakabayashi, S. Niwa*, K. Tsunoda**, J. Lin, A. Shimada, M. Izuha*, T. Aoyama*, H. Tomita*, K. Eguchi* and K. Hieda*, Fujitsu Limited, Yokohama, Japan and *Toshiba Corporation, Yokohama, Japan and **Fujitsu Laboratories Limited, Yokohama, Japan

2:45 p.m.

A New Cell Technology for the Scalable BST Capacitor Using Damascene-formed Pedestal Electrode with a [Pt-Ir] Alloy Coating,

11.4

H. Itoh, Y. Tsunemine, A. Yutani, T. Okudaira, K. Kashihara, M. Inuishi, M. Yamamuka, T. Kawahara*, T. Horikawa*, T. Ohmori* and S. Satoh*, Mitsubishi Electric Corporation, Hyogo, Japan

3:10 p.m.

Break

 

SESSION 12 - Tapa II

Gate and S/D Engineering

Wednesday, June 14, 1:30 p.m.

Chairpersons:

G. De Santi, SGS-Thomson Microelectronics
S. Ohnishi, Sharp Corp.

1:30 p.m.

Reliable and Enhanced Performances of Sub-0.1 [m pMOSFETs Doped by Low Biased Plasma Doping,

12.1

D. Lenoble, F. Arnaud*, A. Grouillet, R. Liebert**, S. Walther**, S. Felch***, Z. Fang*** and M. Haond*, France Telecom, Meylan Cedex, France, *Varian SEA Research Center, Palo Alto, CA and **Varian SEA, Gloucester, MA and ***ST Microelectronics, Crolles Cedex, France

1:55 p.m.

Ultra Low Energy Arsenic Implant Limits on Sheet Resistance and Junction Depth,

12.2

R. Kasnavi, P. Griffin and J. Plummer, Stanford University, Stanford, CA

2:20 p.m.

High Performance pMOSFETs with Ni(SixGe1-x) /Poly-Si0.8Ge0.2 Gate,

12.3

J.-H. Ku, C.-J. Choi, S. Song, S. Choi, K. Fujihara, H.-K. Kang, S.-I. Lee, H.-G. Choi* and D.-H. Ko*, Samsung Electronics Company, Ltd., Kyoungki-Do, Korea and *Yonsei University, Seoul, Korea

2:45 p.m.

Low-Leakage and Highly-Reliable 1.5 nm SiON Gate-Dielectric Using Radical Oxynitridation for Sub-0.1 [m CMOS,

12.4

M. Togo, K. Watanabe, T. Yamamoto, N. Ikarashi, K. Shiba, T. Tatsumi, H. Ono, and T. Mogami, NEC Corporation, Kanagawa, Japan

3:10 p.m.

Break

 

SESSION 13 - Tapa I

Advanced Non-Volatile Memory

Wednesday, June 14, 3:25 p.m.

Chairpersons:

M.-R. Lin, AMD,
S.S. Chung, National Chiao Tung University

3:25 p.m.

0.18[m Modular Triple Self-Aligned Embedded Split-Gate Flash Memory,

13.1

R. Mih, J. Harrington, K. Houlihan, H. K. Lee, K. Chan*, J. Johnson**, B. Chen, J. Yan^ A. Schmidt^, C. Gruensfelder^, K. Kim^, D. Shum^, C. Lo#, D. Lee#, A. Levi# and C. Lam, IBM, Hopewell Junction, NY and *IBM, Yorktown Heights, NY and **IBM, Essex Junction, VT and ^Infineon Technologies, Hopewell Junction, NY and #Silicon Storage Technology, Inc., Sunnyvale, CA

3:50 p.m.

Twin MONOS Cell with Dual Control Gates,

13.2

Y. Hayashi, S. Ogura*, T. Saito* and T. Ogura*, Halo LSI, Tsukuba, Japan and *Halo LSI, Wappingers Falls, NY

4:15 p.m.

A Flash EEPROM Cell with Self-Aligned Trench Transistor & Isolation Structure,

13.3

K. Nakagawa, K. Yoshida, S. Masuda, A. Yoshino and I. Sakai, NEC Corporation, Sagamihara, Japan

4:40 p.m.

Split Gate Cell with Phonon Assisted Ballistic CHE Injection,

13.4

T. Saito, S. Ogura, T. Ogura, T. Yuda*, Y. Kawazu*, M. Ikegami*, A. Uchiyama* and T. Ono*, Halo LSI Inc., Wappingers Falls, NY and *Oki Electric Industry Co., Ltd., Tokyo, Japan

 

SESSION 14 - Tapa II

Channel Engineering

Wednesday, June 14, 3:25 p.m.

Chairpersons:

R. Rakkhit, LSI Logic Corp.,
Y.-J. Mii, TSMC

3:25 p.m.

Multiple SiGe Well: A New Channel Architecture for Improving Both NMOS and PMOS Performances,

14.1

J. Alieu, T. Skotnicki, E. Josse, J.-L. Regolini and G. Bremond*, STMicroelectronics, Crolles Cedex, France and *INSA Lyon, Villeurbanne, France

3:50 p.m.

Auger Recombination Enhanced Hot Carrier Degradation in nMOSFETs with Positive Substrate Bias,

14.2

L.P. Chiang, C.W. Tsai, T. Wang, U.C. Liu*, M.C. Wang* and L.C. Hsia*, National Chiao-Tung University, Hsinchu, Taiwan and *UMC, Hsinchu, Taiwan

4:15 p.m.

Impact of Ion Implantation Statistics on VT Fluctuations in MOSFETs: Comparison Between Decaborane and Boron Channel Implants,

14.3

H. Tuinhout, F. Widdershoven, P. Stolk, J. Schmitz, B. Dirks, K. van der Tak, P. Bancken and J. Politiek, Philips Research Laboratories, Eindhoven, The Netherlands

4:40 p.m.

Direct Measurement of Vth Fluctuation Caused by Impurity Positioning,

14.4

T. Tanaka, T. Usuki, Y. Momiyama and T. Sugii, Fujitsu Laboratories Ltd., Atsugi, Japan


 

RUMP SESSIONS

Tapa III, Honolulu I, II, III

Wednesday, June 14, 8:00 p.m. - 10:00 p.m.

Technology and Circuits Joint Rump Session

Organizers:

S. Borkar, Intel
T. Kozawa, STARC

RJ1

Circuit and System Technology in the year 2010

Tapa III

 

Moderators:

 

Technology:

Circuits:

 

J. Woo, UCLA
T. Shibata, Univ. of Tokyo

S. Borkar, Intel
T. Kozawa, STARC

 

What kind of systems will be prevailing in the year 2010? Will they be ultra powerful PCs with multi-GHz processors, ultra reality Play Station-X, or ultra intelligent cellular phones? Will high performance chips in such systems integrate 100's of millions (if not billions) of transistors, having feature sizes below 100 nm? Will these systems be monolithic special function chips such as processors, or more likely to integrate diverse functions, towards system-on-a-chip (SOC)? What circuit, device, interconnect, and process technologies will they employ? Technology scaling in the next decade will face even greater challenges. Transistor leakage currents will increase dramatically to satisfy the performance demand. Interconnects will scale to advance integration, but RC delays will start dominating even more. Copper interconnects and low-K dielectrics will ease the burden somewhat, and SOI and derivative silicon technologies will help. But will these advances keep up with the demand? Circuit design, in the presence of high leakage and worse RC's, will be ever more challenging. What will happen to the traditional high performance circuits such as Domino-will they have a future? What will these chips look like in terms of performance, power, and size, and where will these chips get used? If the industry leans towards SOC, then what technology and circuit challenges lay ahead? The panel consisting of technology, circuit, and system experts will discuss these issues, and enlighten us with their thoughts.

 

Technology Rump Sessions

Organizers:

J. Woo, University of California
T. Kunio, NEC Corp.

R2

DRAM scaling challenges and innovations between now and 2010: How far can the DRAM cell shrink?

Honolulu I

 

Moderators:

C. Dennison, Micron Technology,
F. Horiguchi, Toshiba

 

For the last 25 years the continual scaling of DRAM cell size and the resulting exponential 27% price reduction per year has been one of the key driving factors for the overall explosive growth of the entire microelectronics and computer industries. However, a recurring question that comes up is - how long will the DRAM cell continue to scale? The panelists will discuss and debate the key technology challenges such as modifications in cell capacitor structure and dielectric material along with impact and probability of cell architecture change from current 8F2 folded bit line to 4F2 and below as forecasted by SIA's 1999 International Technology Roadmap for Semiconductors.

 

R3

Lithography for sub-100nm, optical vs. non-optical

Honolulu II

 

Moderators:

Christopher Spence, AMD,
Shinji Okazaki, ASET

 

Current 248nm optical lithography is the mainstay of manufacturing for the 180nm design rule generation and is expected to extend to 130nm design rules. 193nm lithography will take us to 100nm design rules. Researchers are currently working on Extreme Ultra Violet (EUV) and Electron Projection Lithography (EPL) that will allow us to manufacture design rules of 50nm and below. Unfortunately, if we are to keep pace with the IST technology roadmap there appears to be a gap in lithography technology between the 100nm and 50nm design rules. There are several ways in which this gap may be bridged:

It is most likely that the third option, i.e. incrementally extending existing technology, will be the realistic solution. There are enormous challenges to the lens and stepper makers if we are to obtain good CD control and tight overlay, however, the lens issues are probably better understood for optical lenses than EUV mirrors and although overlay is very challenging all future lithography systems must achieve the same overlay tolerance.

193nm exposure has already demonstrated resolution of 80nm line/space patterns using Alternating PSM masks. Unfortunately, although it is possible to resolve line/space patterns, i.e. 1-D patterns with some CD control, 2-D patterns, e.g. line ends and corners have much worse CD control. Consequently it will no longer be possible to simply shrink designs from the previous technology. In addition, when using scattering bars certain pitches may have worse CD control than others and must be "forbidden. In the case of PSM, some layout choices may lead to designs that cannot be phase shifted and must be avoided. In dense layouts, phase shift patterns may lead to enhanced line-end pull back. Other approaches, such as IDEAL proposed by Canon, require designs to be laid out on a fixed grid. To successfully extend 193nm lithography to support 70nm design rules will require:

This panel will provide an overview of current and future lithography technologies and discuss resolution enhancement techniques with particular emphasis on the issues involved in integrating them into layout and mask design. It is hoped that we can initiate a discussion between process engineers and designers that will allow us to extend optical lithography as far a possible.

 

R4

Novel Structures and Processes for Continued MOSFET Scaling: What, When, and Whether?

Honolulu III

 

Moderators:

Don Monroe, Bell Labs, Lucent Technologies,
Inuishi Masahide, Mitsubishi Electric Co.

 

Scaling MOSFET gate lengths to 70 nm and below will require continued reduction in spacer thickness, junction depth, and lateral dopant gradient. The doping, especially of PMOSFETs, is facing fundamental limits. What are the real requirements on the source/drain extensions and channel? Can the doping schemes that have served for the past decade continue to meet these requirements? How much improvement can be achieved by doping source and drain differently? If mid-gap metal gates are required, how much will the minimum gate length increase? Are there proposed novel structures that provide a way out?

 


SESSION 15 - Tapa I

Technologies For System-on-a-Chip

Thursday, June 15, 8:30 a.m.

Chairpersons:

L. Su, IBM,
T. Nakamura, Rohm

8:30 a.m.

A CMOS Technology Platform for 0.13[ m Generation SOC (System on a Chip),

15.1

H. Yoshimura, T. Nakayama, M. Nishigohri, M. Inohara, K. Miyashita, E. Morifuji, A. Oishi, H. Kawashima, M. Habu, H. Koike, H. Takato, Y. Toyoshima and H. Ishiuchi, Toshiba Corporation, Kanagawa, Japan

8:55 a.m.

A 0.15 [ m CMOS Foundry Technology with 0.1 [ m Devices for High Performance Applications,

15.2

C. Diaz, M. Chang, W. Chen, M. Chiang, H. Su, S. Chang, P. Lu, C. Hu, K. Pan, C. Yang, L. Chen, C. Su, C. Wu, Ch. Wang, C.C. Wang, J. Shih, H. Hsieh, H. Tao, S. Jang, M. Yu, S. Shue, B. Chen, T. Chang, C. Hou, B.K. Liew, K.H. Lee and Y.C. Sun, Taiwan Semiconductor Manufacturing Company, Taiwan, R.O.C.

 9:20 a.m.

A Triple Gate Oxide CMOS Technology Using Fluorine Implant for System-On-A-Chip,

15.3

Y. Goto, K. Imai, E. Hasegawa, T. Ohashi, N. Kimizuka, T. Toda, N. Hamanaka, and T. Horiuchi, NEC Corporation, Kanagawa, Japan

 9:45 a.m.

A 180nm Copper/Low-k CMOS Technology with Dual Gate Oxide Optimized for Low Power and Low Cost Consumer Wireless Applications,

15.4

G. C-F Yeap, F. Nkansah, J. Chen, S. Jallepalli, D. Pham, T. Lii, A. Nangia, P. Le, D. Hall, D. Menke, J. Sun, A. Das, P. Gilbert, F. Huang, J. Sturtevant, K. Green, J. Lu, J. Benavidas, E. Banks, J. Chung, and C. Lage, Motorola, Inc., Austin, TX

10:10 a.m.

Break

 

SESSION 16 - HONOLULU SUITE

High Performance RF/Analog

Thursday, June 15, 8:30 a.m.

Chairpersons:

C. Van Der Poel, Philips Research Labs,
T. Shibata, University of Tokyo

8:30 a.m.

Impact of 0.18 [ m SOI CMOS Technology Using Hybrid Trench Isolation with High Resistivity Substrate on Embedded RF/Analog Applications,

16.1

S. Maeda, Y. Wada, K. Yamamoto, H. Komurasaki, T. Matsumoto, Y. Hirano, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa and M. Inuishi, Mitsubishi Electric Corporation, Hyogo, Japan

8:55 a.m.

Well-Controlled, Selectively Under-Etched Si/SiGe Gates for RF and High Performance CMOS,

16.2

T. Skotnicki, M. Jurczak*, J. Martins, M. Paoli*, B. Tormen, R. Pantel*, C. Hernandez, I. Campidelli*, E. Josse*, G. Ricci* and J. Galvier, STMicroelectronics, Crolles, France and *France Telecom, Meylan, France

 9:20 a.m.

CMOS with Active Well Bias for Low-Power and RF/Analog Applications,

16.3

C. Wann, J. Harrington, R. Mih, S. Biesemans, K. Han, R. Dennard*, O. Prigge**, C. Lin**, R. Mahnkopf** and B. Chen, IBM SRDC, Hopewell Junction, NY and *IBM TJ Watson Research Center, Yorktown Heights, NY and **Infineon Technologies, Hopewell Junction, NY

 9:45 a.m.

An Epitaxial Channel MOSFET for Improving Flicker Noise Under Low Supply Voltage,

16.4

T. Ohguro, R. Hasumi, T. Ishikawa, M. Nishigori, H. Oyamatsu and F. Matsuoka, Toshiba Corporation, Kanagawa, Japan

10:10 a.m.

Break

 

SESSION 17 - Tapa I

Advanced SRAM Technology

Thursday, June 15, 10:25 a.m.

Chairpersons:

J. Watt, Cypress Semiconductor
F. Matsuoka, Toshiba Corp.

10:25 a.m.

A 0.99-[m2 Loadless Four-Transistor SRAM Cell in 0.13-[ m Generation CMOS Technology,

17.1

S. Masuoka, K. Noda, S. Ito, K. Matsui, K. Imai, N. Yasuzato, H. Kawamoto, N. Ikezawa, K. Ando, S. Koyama, T. Tamura, Y. Yamada, and T. Horiuchi, NEC Corporation, Kanagawa, Japan

10:50 a.m.

A Highly Versatile 0.18[ m CMOS Technology with Dense Embedded SRAM,

17.2

M. Bhat, S. Shi, P. Grudowski, C. Feng, B. Lee, R. Nagabushnam, J. Moench, C. Gunderson, P. Schani, L. Day, S. Bishop, H. Tian, J. Chung, C. Lage, J. Ellis, N. Herr, P. Gilbert, A. Das, F. Nkanasah, M. Woo, M. Wilson, D. Derr, L. Terpolilli, K. Weidermann, R. Stout, A. Hamilton, T. Lii, F. Huang, K. Cox and J. Scott, Motorola, Inc., Austin, TX

11:15 a.m.

A Novel Logic Compatible Gain Cell with Two Transistors and One Capacitor,

17.3

N. Ikeda, T. Terano, H. Moriya, T. Emori and T. Kobayashi, Sony Corporation, Kanagawa-Ken, Japan

11:40 a.m.

A Partially Depleted 1.8V SOI CMOS SRAM Technology Featuring a 3.77[m2 Cell,

17.4

K. Cox, J. Scott, S. Bishop, M. Bhat, B. Nettleton, D. Pan, M. Hamilton, D. Chang, L. Day and P. Schani, Motorola, Inc., Austin, TX

12:05 p.m.

Lunch

 

SESSION 18 - HONOLULU SUITE

Device Technology

Thursday, June 15, 10:25 a.m.

Chairpersons:

S. Thompson, Intel Corp.
H. Hanafusa, Sanyo Electric

10:25 a.m.

Scaling Challenges and Device Design Requirements for High Performance Sub-50nm Gate Length Planar CMOS Transistors,

18.1

T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi and M. Bohr, Intel Corp., Hillsboro, OR

10:50 a.m.

Advantage of Radical Oxidation for Improving Reliability of Ultra-Thin Gate Oxide,

18.2

Y. Saito, K. Sekine, N. Ueda*, M. Hirayama, S. Sugawa and T. Ohmi**, Tohoku University, Sendai, Japan and *Sharp Corp., Nara, Japan and **Tohoku University, Sendai, Japan

11:15 a.m.

Advanced Shallow Trench Isolation to Suppress the Inverse Narrow Channel Effects for 0.24[ m Pitch Isolation and Beyond,

18.3

K. Horita, T. Kuroi, Y. Itoh, K. Shiozawa, K. Eikyu, K. Goto, Y. Inoue and M. Inuishi, Mitsubishi Electric Corporation, Hyogo, Japan

11:40 a.m.

Silicide and Shallow Trench Isolation Line Width Dependent Stress Induced Junction Leakage,

18.4

A. Steegen, A. Lauwers, M. de Potter, G. Badenes, R. Rooyackers and K. Maex, IMEC, Leuven

12:05 p.m.

Lunch

 

SESSION 19 - Tapa I

High Performance CMOS

Thursday, June 15, 1:30 p.m.

Chairpersons:

G. Bomchil, France Telecom, CNET,
T. Tsuchiya, Shimane University

1:30 p.m.

A High Performance 0.13[ m SOI CMOS Technology with Cu Interconnects and Low-k BEOL Dielectric,

19.1

P. Smeys, V. McGahay, I. Yang, J. Adkisson, K. Beyer, O. Bula, Z. Chen, B. Chu, J. Culp, S. Das, A. Eckert, L. Hadel, M. Hargrove, J. Herman, L. Lin, R. Mann, E. Maciejewski, S. Narasimha, P. O'Neil, S. Rauch, D. Ryan, J. Toomey, L. Tsou, P. Varekamp, R. Wachnik, T. Wagner, S. Wu, C. Yu, P. Agnello, J. Connolly, S. Crowder, C. Davis, R. Ferguson, A. Sekiguchi, L. Su, R. Goldblatt and T.C. Chen, IBM SRDC, Hopewell Junction, NY

1:55 p.m.

High-Performance 80-nm Gate Length SOI-CMOS Technology with Copper and Very-Low-k Interconnects,

19.2

K. Sukegawa, M. Yamaji, K. Yoshie, K. Furumochi, T. Maruyama, H. Morioka, N. Naori, T. Kubo, H. Kanata, M. Kai, S. Satoh, T. Izawa and K. Kubota, Fujitsu Ltd., Mie, Japan

2:20 p.m.

Sub-0.1[m CMOS with Source/Drain Extension Spacer Formed Using Nitrogen Implantation Prior to Thick Gate Re-Oxidation,

19.3

J.C. Hu, A. Chatterjee, M. Mehrotra, J. Xu, W.T. Shiau and M. Rodder, Texas Instruments, Dallas, TX

2:45 p.m.

Design of Sub-100nm CMOSFETs: Gate Dielectrics and Channel Engineering,

19.4

S. Song, W.S. Kim, J.S. Lee, T.H. Choe, J.H. Choi, M.S. Kang, U.I. Chung, N.I. Lee, K. Fujihara, H.K. Kang, S.I. Lee and M.Y. Lee, Samsung Electronics Company, Ltd., Kyounki-Do, Korea

3:10 p.m.

Break

 

SESSION 20 - HONOLULU SUITE

Modeling

Thursday, June 15, 1:30 p.m.

Chairpersons:

R. Nowak, Applied Materials
S. Odanaka, Matsushita Semiconductor

1:30 p.m.

An Integrated Architecture for Global Interconnects in a Gigascale System-on-a-Chip (GSoC),

20.1

P. Zarkesh-Ha and J. Meindl, Georgia Institute of Technology, Atlanta, GA

1:55 p.m.

An Accurate Non-Quasistatic MOSFET Model for Simulation of RF and High Speed Circuits,

20.2

X. Jin, K. Cao, J-J Ou, W. Liu, Y. Cheng*, M. Matloubian* and C. Hu, University of California, Berkeley, CA and *Conexant Systems, Inc., Newport Beach, CA

2:20 p.m.

Modeling Gate and Substrate Currents due to Conduction- and Valence-Band Electron and Hole Tunneling,

20.3

W-C Lee and C. Hu, University of California, Berkeley, CA

2:45 p.m.

Vdd Impact on Propagation Pulse Width Variation in PD SOI Circuits,

20.4

B. Min, G. Workman, D. Chang, O. Zia, Y. Yu, R. Widenhofer, B. Simon, N. Cave, H. Sanchez, S. Veeraraghavan, M. Mendicino and B. Yeargain, Motorola, Austin, TX

3:10 p.m.

Break

 

SESSION 21 - Tapa I

Advanced SOI Devices and Modeling

Thursday, June 15, 3:25 p.m.

Chairpersons:

M. Cao, PDF Solutions,
Y. Omura, Kansai University

3:25 p.m.

Scalability Revisited: 100nm PD-SOI Transistors and Implications for 50nm Devices,

21.1

K. Mistry, T. Ghani, M. Armstrong, S. Tyagi, P. Packan, S. Thompson, S. Yu and M. Bohr, Intel Corp., Hillsboro, OR

3:50 p.m.

A Partially-Depleted SOI Compact Model - Formulation and Parameter Extraction,

21.2

S.K.H. Fung, L. Wagner, M. Sherony, N. Zamdmer, J. Sleight, M. Michel, E. Leobandung, S.H. Lo, T.C. Chen and F. Assaderaghi, IBM SRDC, Hopewell Junction, NY

4:15 p.m.

A Compact FD-SOI MOSFETs Fabrication Process Featuring SixGe1-x Gate and Damascene-Dummy SAC,

21.3

D. Hisamoto, T. Kachi, S. Tsujikawa, A. Miyauchi, K. Kusukawa, N. Sakuma, Y. Homma, N. Yokoyama, F. Ootsuka, and T. Onai, Hitachi Limited, Tokyo, Japan

4:40 p.m.

Advanced SOI-MOSFETs with Strained-Si Channel for High Speed CMOS - Electron/Hole Mobility Enhancement,

21.4

T. Mizuno, N. Sugiyama, H. Satake and S. Takagi, Toshiba Corporation, Yokohama, Japan

 

SESSION 22 - HONOLULU SUITE

Deep Sub-Micron Reliability

Thursday, June 15, 3:25 p.m.

Chairpersons:

J. Woo, University of California,
S.S. Chung, National Chiao Tung University

3:25 p.m.

Gate Oxide Breakdown Under Current Limited Constant Voltage Stress,

22.1

B. Linder, J. Stathis, R. Wachnik*, E. Wu**, S. Cohen, A. Ray* and A. Vayshenker*, IBM Research Division, Yorktown Heights, NY and *IBM Microelectronics Division, Hopewell Junction, NY and **IBM Microelectronics Division, Essex Junction, VT

3:50 p.m.

Impacts of Strained SiO2 on TDDB Lifetime Projection,

22.2

Y. Harada, K. Eriguchi, M. Niwa, T. Watanabe* and I. Ohdomari*, Matsushita Electronics Corporation, Kyoto, Japan and *Waseda University, Tokyo, Japan

4:15 p.m.

TBD Prediction from Measurements at Low Field and Room Temperature using a New Estimator,

22.3

A. Ghetti, J. Bude and G. Weber, Lucent Technologies, Bell Laboratories, Murray Hill, NJ

4:40 p.m.

Practical Benefits of the Electromigration Short-Length Effect, Including a New Design Rule Methodology and an Electromigration Resistant Power Grid with Enhanced Wireability,

22.4

R. Wachnik, R. Filippi, T. Shaw* and P. Lin**, IBM Microelectronics Division, Hopewell Junction, NY and *IBM Research Division, Yorktown Heights, NY and **IBM Server Group, Poughkeepsie, NY

 


GENERAL INFORMATION

 

SCOPE OF SYMPOSIUM

The Symposium covers all aspects of VLSI technology, such as: new functional devices including quantum effect devices with possible VLSI implementation; materials innovation for MOSFET and interconnect in VLSI; advanced lithography and fine patterning technologies for high density VLSI; process/device modeling and VLSI manufacturing control; packaging and reliability of VLSI devices; and theories and fundamentals related to the above devices.

 

REGISTRATION INFORMATION

The deadline to register is May 19, 2000. After May 19, 2000 you must register on-site. If you register on-site, an additional $75 will be added to the registration fees. Payment of the registration fee entitles the registrant to one copy of the Technical Digest, one CD-ROM, three Continental breakfasts, all coffee breaks, one banquet and one reception ticket.

 

 

Member

NonMember

Students

 

US$

Yen

US$

Yen

US$

Yen

Technology

Short Course

$275

¥31000

$300

¥33000

$75

¥9000

Statistical Metrology

$185

¥21000

$225

¥25000

$175

¥20000

Technology

Symposium

$395

¥45000

$445

¥50000

$195

¥22000

Tech/Circuits

Symposia

$695

¥80000

$795

¥90000

$390

¥43000

Circuits Short Course

$275

¥31000

$300

¥33000

$75

¥9000

Circuits Symposium

$395

¥45000

$445

¥50000

$195

¥22000

Digests

$75

¥9000

$75

¥9000

$75

¥9000

Add'l Short CourseBook

$40

¥5000

$40

¥5000

$40

¥5000

Banquet Tickets

$75

¥9000

$75

¥9000

$75

¥9000

 

Payment in US dollars is strongly encouraged by the use of credit cards (MasterCard/Visa) and through the American Secretariat. However, for special cases where payment in Japanese Yen is required, please remit your payment through the Japanese Secretariat.

 

REGISTRATION VIA AMERICAN SECRETARIAT

Credit Cards (MasterCard/Visa), personal checks, company checks or traveler’s checks payable to the 2000 VLSI Symposia in U.S. Dollars are the only acceptable forms of payment. All checks must be drawn on U.S. banks. Registration not conforming to these guidelines will be returned. Please complete the Registration Card (see centerfold) and return with payment of the appropriate registration fees no later than May 19, 2000 to Widerkehr and Associates, 101 Lakeforest Boulevard, Suite 400B, Gaithersburg, MD 20877 USA.

 

REGISTRATION VIA JAPANESE SECRETARIAT

Bank drafts, bank transfers and company checks payable to the VLSI Symposia in Japanese Yen are the only acceptable forms of payment. Personal checks and credit cards will NOT be accepted. Please complete the Registration Card (see centerfold) and return with payment of the appropriate registration fees NO LATER THAN MAY 19, 2000 to the Business Center for Academic Societies Japan, Conference Dept., 5-16-9 Honkomagome, Bunkyo-ku, Tokyo 113-8622, Japan.

 

CANCELLATION POLICY

All requests for refunds for registrations paid in US dollars must be made in writing and submitted to Widerkehr and Associates, 101 Lakeforest Boulevard, Suite 400B, Gaithersburg, MD 20877 USA. All requests for refunds for registrations paid in Japanese Yen also must be made in writing and submitted to the Business Center for Academic Societies Japan, 5-16-9 Honkomagome, Bunkyo-ku, Tokyo 113-8622, Japan. Refunds, minus a $30.00 or ¥3300 processing fee, will be issued for cancellations received on or before May 26, 2000. No refunds will be issued for cancellations received after May 26, 2000. All refunds will be processed after the Symposia.

 

SYMPOSIA COORDINATION CENTER

The Symposia Coordination Center, located in the Palace Lounge Lobby will be open as follows:

Symposium on VLSI Technology

Sunday, June 11

5:00 pm - 8:00 pm

Monday, June 12

7:30 am - 5:00 pm

Tuesday, June 13

7:30 am - 5:00 pm

Wednesday, June 14

7:30 am - 5:00 pm

Thursday, June 15

7:30 am - 5:00 pm

Symposium on VLSI Circuits

Wednesday, June 14

7:30 am - 5:00 pm

Thursday, June 15

7:30 am - 5:00 pm

Friday, June 16

8:00 am - 5:00 pm

Saturday, June 17

8:00 am - 12:00 noon

 

 VLSI TECHNOLOGY SYMPOSIUM RECEPTION

A reception will be held on Monday, June 12 from 7:00 pm to 9:00 pm on the Lagoon Green.

 

VLSI TECHNOLOGY SYMPOSIUM BANQUET

The 2000 Symposium on VLSI Technology Banquet will be held on Tuesday, June 13 on the Lagoon Green from 7:00 pm to 9:00 pm. Banquet tickets for accompanying guests can be purchased at the Registration desk in the Palace Lounge Lobby.

 

SPEAKER PREPARATION CENTER

There will be a designated Speaker Preparation Room. Specifics will be available at the Registration Desk located in the Palace Lounge Lobby.

 

TECHNICAL DIGEST

Registrants will receive (1) copy of the Technical Digest and (1) copy of the CD-Rom when they pick up their Symposium materials at the Registration Desk. Additional copies of the Technical Digest will be available on-site for $75/Digest. Following the Symposium, additional copies of the Technical Digest will be available through IEEE Single Copy Sales, 445 Hoes Lane, Piscataway, NJ 08855, USA (Toll free) 1-800-678-4333.

 

TRAVEL EXPENSE SUPPORT

Requests for partial travel expense support for students who are presenting papers should be sent to: Craig Lage, Motorola, Inc., 3501 Ed Bluestein Blvd, MD K-10, Austin, TX 78721 no later than April 26, 2000. All travel support will be paid after the Symposia.

 

MESSAGE CENTER

The Message Board will be located in the Palace Lounge Lobby adjacent to the Registration Desk. Please advise those who wish to reach you during the day to contact the Hilton Hawaiian Village at 808-949-4321 and request the VLSI Symposia Message Desk. Facsimiles clearly marked with both the recipient's name and the name of the Symposia may be sent to 808-947-7914. Please check the Message Board regularly, since there will be no delivery service provided.

 

GUEST ORIENTATION

A guest orientation with continental breakfast will be held at 9:00 a.m., Tuesday, June 13 in the Iolani IV room. Sightseeing information will be provided.

 

STATISTICAL METROLOGY WORKSHOP

The Fifth International Workshop on Statistical Metrology will be held on Sunday, June 11, 2000 in Honolulu, Hawaii. The Workshop will be held in association with and precede the 2000 Symposium on VLSI Technology. This Workshop is an opportunity to learn about state of the art statistical methods for the design of VLSI process, devices, and circuits. This year’s agenda features a keynote address by Prof. Tadahiro Ohmi, "Perfect Scientific Manufacturing Free from Fluctuations" and three tutorial talks by leading workers in the field. The talks will be Dr. Steve Duvall, Intel, on statistical circuit modeling; Dr. Sani Nassif, IBM, on statistical process models; and Dr. Andrzej Strojwas, PDF Solutions, on yield modeling.

For the first time, this one-day Workshop integrates tutorials with the technical sessions in order to (1) raise process, device and circuit designer’s awareness about variation and statistical issues in design; and (2) provide a forum for discussion among researchers working in this field. The final program will be available on the web by March 31, 2000 at: http://www-mtl.mit.edu/StatMet2000/

 


To obtain an Advance Program and other general information or to be placed on the Symposia mailing list, please contact:

2000 Symposia on VLSI Technology and Circuits
Widerkehr and Associates
101 Lakeforest Boulevard, Suite 400B
Gaithersburg, MD 20877 USA
Phone: +1-301-527-0900 Fax: +1-301-527-0994.
Email: vlsi00@aol.com

 

2000 VLSI TECHNOLOGY SYMPOSIUM COMMITTEE

Chairman:

 

 

Antonio R. Alvarez

Cypress Semiconductor

Co-Chairman:

 

 

Eiji Takeda

Hitachi

Program Chairman:

 

 

Craig Lage

Motorola, Inc.

Program Co-Chairman:

 

 

Tadashi Nishimura

Mitsubishi Electric

Secretary:

 

 

Bob Havemann

TI/SEMATECH

 

Makoto Ohkura

Hitachi

Publications:

 

 

Fumitomo Matsuoka

Toshiba Corp.

Publicity:

 

 

Makoto Ohkura

Hitachi

Treasurer:

 

 

Bob Havemann

TI/SEMATECH

 

Shinji Odanaka

Matsushita Semiconductor

Local Arrangements:

 

 

Yuan Taur

IBM Research Center

 

Hiroshi Hanafusa

Sanyo Electric

 

Kazunori Nakahara

Sharp Corp.

 Short Course Organizer:

 

 

Simon Wong

Stanford University

 

Seiichiro Kawamura

Fujitsu

 Rump Session Organizer:

 

 

Jason Woo

University of California

 

Takemitsu Kunio

NEC Corp.

 

EXECUTIVE COMMITTEES

IEEE Chairman:

 

 

James T. Clemens

Bell Labs, Lucent Technologies

Members:

 

 

Asad Abidi

UCLA

 

Antonio Alvarez

Cypress Semiconductor

 

Bill Bidermann

S3 Inc.

 

Gilbert DeClerck

IMEC

 

Youssef El-Mansy

Intel Corporation

 

Richard Jaeger

Auburn University

 

Nino Masnari

North Carolina State Univ.

 

Yoshi Nishi

Texas Instruments

 

Kevin O'Connor

Bell Labs, Lucent Technologies

 

Bill Siu

Intel Corp.

 

Charles Sodini

Massachusetts Institute of Technology

 

Peter Verhofstadt

Semiconductor Research Corporation

 

Ian Young

Intel Corp.

JSAP Chairman:

 

 

Takuo Sugano

Toyo University

Co-Chairman:

 

 

Susumu Kohyama

Toshiba

Members:

 

 

Chun-Yen Chang

National Chiao Tung University

 

Masao Fukuma

NEC

 

Yutaka Hayashi

University of Tsukuba

 

Koichiro Hoh

University of Tokyo

 

Chang-Gyu Hwang

Samsung Electronics

 

Hajime Ishikawa

Fujitsu Laboratories

 

Atsushi Iwata

Hiroshima University

 

Masakazu Kakumu

Toshiba

 

Choong-Ki Kim

KAIST

 

Yojiro Mano

Matsushita Electric

 

Toshiaki Masuhara

Hitachi

 

Akihiko Morino

NEC

 

Tadashi Nishimura

Mitsubishi Electric

 

Tsunenori Sakamoto

Electrotechnical Laboratory

 

Takayasu Sakurai

University of Tokyo

 

Masao Taguchi

Fujitsu

 

Eiji Takeda

Hitachi

 

Ken Takeya

NTT

 

Fang-Churng Tseng

TSMC

 

Masakazu Yamashina

NEC

 

TECHNICAL PROGRAM COMMITTEES

NORTH AMERICA/EUROPE

Chairman:

 

 

Craig Lage

Motorola, Inc.

Members:

 

 

William Arnold

ASM Lithography

 

Guillermo Bomchil

France Telecom

 

Min Cao

PDF Solutions

 

Ludo Deferm

IMEC

 

Roger DeKeersmaecker

IMEC

 

Chuck Dennison

Micron Technology

 

Giorgio De Santi

SGS-Thomson Micro.

 

Robert Havemann

Texas Instruments

 

Jack Lee

University of Texas

 

Min-Ren Lin

AMD

 

Reinhard Mahnkopf

Siemens AG

 

Romek Nowak

Applied Materials

 

Carl Osburn

N. Carolina State University

 

C.S. Pai

Lucent Technologies, Bell Labs

 

Rajat Rakkhit

LSI Logic Corp.

 

Tom Seidel

Genus Corporation

 

Lisa Su

IBM

 

Yuan Taur

IBM

 

Scott Thompson

Intel Corporation

 

Carel van der Poel

Philips Research Labs

 

Jeff Watt

Cypress Semiconductor

 

Simon Wong

Stanford University

 

Jason Woo

University of California

JAPAN/FAR EAST

Co-Chairman:

 

 

Tadashi Nishimura

Mitsubishi Electric

Members:

 

 

Steve Chung

National Chiao Tung University

 

Takahisa Eimori

Mitsubishi Electric

 

Hiroshi Hanafusa

Sanyo Electric

 

Jeong-Mo Hwang

Hyundai Microelectronics

 

Jiro Ida

Oki Electric

 

Seiichiro Kawamura

Fujitsu

 

Takemitsu Kunio

NEC

 

Hideaki Kuroda

Sony

 

Sang-In Lee

Samsung Electronics

 

Teyin Mark Liu

TSMC

 

Fumitomo Matsuoka

Toshiba

 

Takashi Nakamura

Rohm

 

Shinji Odanaka

Matsushita Semiconductor

 

Makoto Ohkura

Hitachi

 

Yasuhisa Omura

Kansai University

 

Shigeo Onishi

Sharp

 

Kentaro Shibahara

Hiroshima University

 

Tadashi Shibata

University of Tokyo

 

Eiichi Suzuki

Electrotechnical Lab.

 

Toshiaki Tsuchiya

Shimane University


 

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