Short Course 1 (Technology)

* If you encounter menus do not work upon clicking, delete your browser's cache.

Advanced Process and Device Technology toward 2nm-CMOS and Emerging Memory

Moderators: Kazuhiko Endo (AIST) and Suman Datta (U. Notre Dame)

This short course addresses advanced process and device technology toward 2nm-CMOS. Advanced transistors such as nanosheets and CFET, advanced interconnects and contact, metrology challenges are covered. In addition, emerging memories and DRAM technologies including ReRAM, PCM, FeRAM will be shown.

Live Q&A Session: June 14, 7:00AM-8:30AM (JST)

CMOS Device Technology for the Next Decade, Jin Cai, TSMC

The remarkable advancement of CMOS technology over the last 50 years has enabled billion-transistor computing power at fingertips. Insatiable societal demand for more computing power will drive higher density and more power efficient technology development in the next decade. In this short course, I will start with a review of the state-of-the-art FinFET transistors which enabled CMOS scaling in the last decade. Nanosheet transistor is the next device architecture being pursued to replace FinFET. I will discuss its benefits and opportunities. Stacked 3D transistors can enable further density scaling beyond FinFET and nanosheet, but need to overcome challenges in process complexity, power density and heat dissipation. In the last part, I will discuss alternative device architectures and channel materials that have potential to complement and improve silicon CMOS. Together with improved memory density and interconnect bandwidth, advanced logic technology will continue to improve system level performance in the next decade.

Nanosheet Device Architectures to Enable CMOS Scaling in 3nm and beyond: Nanosheet, Forksheet and CFET, Naoto Horiguchi, imec

FinFET is coming to its scaling limit and Nanosheet device architecture is taking over FinFET’s position in CMOS industry gradually. In this presentation, we will review CMOS scaling scenarios and challenges in 3nm and beyond by using Nanosheet device architectures, such as Nanosheet, Forksheet and CFET. Nanosheet has advantages in wider effective transistor width/footprint, good electrostatics, and flexible transistor width over FinFET. Forksheet is an advanced nanosheet architecture, which has a dielectric wall between NMOS and PMOS. The dielectric wall enables smaller N-P space and smaller Miller capacitance in Forksheet than Nanosheet. Nanosheet and Forksheet have common integration challenges as compared to FinFET, such as Si/SiGe multilayer fin formation at low temperature, sub-fin leakage suppression, SD epi with inner spacer, nanosheet channel release and gate-last integration with GAA channel. CFET is an ultimate CMOS device architecture, which has stacked NMOS and PMOS. It enables CMOS in single device footprint. For CFET, vertical N&P integration is necessary in SD, contact and gate stack. There are 2 possible integration schemes for the vertical integration: monolithic and sequential integration. Monolithic integration has advantages in cost and parasitics. But it has challenges in vertical process control in SD, contact and gate stack by using deposition, planarization and etch back. Sequential integration simplifies the vertical integration, which consists of bottom device integration, top device channel wafer transfer, and top device integration. But it has challenges in wafer transfer defect control & boding oxide thickness scaling, top-bottom gate connection, low temperature top device integration.

Extension of Cu Interconnects and Considerations for Post-Cu Alternative Metals in Advanced Nodes, Koichi Motoyama, IBM

Due to continued scaling of BEOL Cu interconnect dimensions, achieving void-free Cu fill has proven to be very challenging. To improve Cu fill performance, several novel methods such as Cu reflow fill have been developed and incorporated. However, even with decent Cu fill capability, line resistance increase and EM performance degradation remain as two major issues for Cu interconnects at small dimensions that need to be addressed to extend Cu interconnects towards future nodes. In parallel with the intensive effort to extend Cu as an interconnect metal, post-Cu alternative metals such as platinum group metals are being considered with keen interest because of their favorable electron scattering behavior (which should alleviate the line R increase caused by size effects) and higher melting point (which should lead to better EM performance). In this presentation, several key approaches to overcome these two major challenges of line R increase and EM degradation for extending Cu interconnects are shared. Furthermore, various aspects of post-Cu alternative metal interconnects are discussed.

Contact Module Engineering for Advanced CMOS Technologies: Key Concepts, Engineering Techniques and Device Integration Challenges, Nicolas Breil, Applied Materials

As CMOS technology dimensions continue to scale, the contact module resistance becomes a fundamental bottleneck for the device performance improvement. After reviewing the historical evolution of the silicide technology, we will define the key components of the contact module and identify their respective impact on the device performance. We will then review the process technologies available for the engineering of the contact module. We will analyze several recent technical breakthroughs and offer some perspectives and directions towards upcoming architectures.

Metrology Challenges Towards 2nm Technology Node, Masami Ikoda, Hitachi High Tech.

Device patterns have continuously been shrinking in X, Y and Z directions concurrently following Moore’s law. According to IRDS (International Roadmap for Devices and Systems), mainstream of logic-device structure will change from Fin to LGAA (Lateral Gate-all-around) at 2-nm node. Minimum values of lateral and vertical pitches of nanowire or nanosheet channels in the LGAA-FETs are expected to be as small as 22 nm and 18 nm, respectively. The structural change to LGAA-FET generates new requirements for metrology, i.e., measurements of vertical pitches of stacked nanowire or nanosheet channels in LGAA-FET. For BEOL, with aggressive dimensional scaling, new materials such as Ru or Co will be implemented to decrease the interconnect resistance. Atomic level of measurement precision will be required for the metrology equipment to detect process excursions. This short course overviews the current metrology and the inspection techniques focusing on monitoring the critical dimensions. Efforts to realize atomic level of measurement precision and future metrology solutions towards 2-nm node and beyond, are also introduced.

Emerging Memories and the Applications, Hang-Ting Lue, Macronix

Emerging memories including resistive RAM (ReRAM), phase-change memory (PCM), ferroelectric devices, and novel 3D memory architectures are often the hot topics in semiconductor conferences. In this short course, the progress of each emerging memory devices will be briefly summarized. The major focus is the application including opportunity and challenges. The opportunities are the chances to improve the existing memory technology (DRAM, Flash, SRAM) in some applications, while the challenges and critical comments in terms of product design and marketing competitiveness will be addressed. The bright future is that memory is playing more and more important role in the big data era to support computing system, while people highlights the bottleneck of "memory wall" that raises opportunities to develop new memory technology to enhance the system performances. On the other hand, the existing memory technologies are so powerful and continuously improved, which raises a high barrier for emerging memory devices to turn into a sizable market. This short course aims to provide some general overview and future suggestions.

Key Device Technologies and Challenges for 3D Emerging Non-Volatile Memory, Masumi Saitoh, Kioxia

This short course gives a review of key device technologies and challenges for 3D emerging memory. In this course, "3D" means multi-layer stacking of memory cells, which is a powerful technology booster for higher-density and lower-cost memory. We start from an overview of 3D flash memory, which has been leading aggressive multi-layer stacking of non-volatile memory. Then, we review promising emerging memory applicable to 3D structures: resistive RAM (ReRAM), phase change memory (PCM), and ferroelectric memory. Stacked ReRAM has been proposed for various applications including in-memory computing. PCM integrated with selectors has been intensively developed for high-density cross-point memory. Ferroelectric memory with ferroelectric HfO2 film has been widely studied for various 3D structures such as ferroelectric FET (FeFET), ferroelectric tunnel junction (FTJ) and ferroelectric RAM (FeRAM).

DRAM: Challenges and Opportunities, Koji Hamada, Micron

Connection, Big data & AI are important key roles in modern society with SDGs. Semiconductor technologies can boost the Connection, Big data and AI to create benefit for all the people. Memory is very attractive to drive these areas. To enable this, memory is going to scaling for realizing low power and faster operation. This course focuses DRAM which is one of the key in memory hierarchy. Firstly, fundamental DRAM elements and historical key challenges will be introduced. Toward further scaling technical barriers are getting higher than ever. Recent key process and device challenges such as access device, refresh characteristics, capacitor and CMOS will be discussed.