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Short Course 1 Short Course 2

Tuesday, June 16

VLSI Design for Big Data Management

Presentation Materials

Organizers / Chairs: Yasumoto Tomita, Fujitsu Laboratories LTD. and HenkJan Bergveld, NXP Semiconductors

10:30 am - 10:40 am | Introduction
10:40 am – 11:30 am | The Four Components of Big Data Analytics, K. Olukotun, Stanford University

Abstract: Big data analytics is the process of examining large data sets to uncover hidden patterns and unknown correlations to accelerate scientific discovery or market trends and customer preferences to develop business insights. This talk will describe four of the key components of big data analytics (1) Extraction Transform and Load (ETL) which takes unstructured data and translates it to structured (tabular) data, (2) Query processing which executes queries over structured data (3) Graph analytics for exploring complex relationships in big data, and (4) Machine learning for building statistical models from big data. For each of the four components we will look at example applications, examine the computational and memory access behavior of the core algorithms and understand how well heterogeneous hardware architectures (CPU, GPU, clusters) perform on these algorithms. This understanding will be used to determine how the hardware for future big-data systems should be architected.

Bio: Kunle Olukotun is the Cadence Design Systems Professor in the School of Engineering and Professor of Electrical Engineering and Computer Science at Stanford University. Olukotun is well known as a pioneer in multicore processor design and the leader of the Stanford Hydra chip mutlipocessor (CMP) research project. Olukotun founded Afara Websystems to develop high-throughput, low-power multicore processors for server systems. The Afara multicore processor, called Niagara, was acquired by Sun Microsystems. Niagara derived processors now power all Oracle SPARC-based servers. Olukotun currently directs the Stanford Pervasive Parallelism Lab (PPL), which seeks to proliferate the use of heterogeneous parallelism in all application areas using Domain Specific Languages (DSLs). Olukotun is an ACM Fellow and IEEE Fellow.

11:30 am – 12:20 pm | CPU Design Challenges for Big-Data, S. Borkar, Intel Corporation

Abstract: Internet collects vast amount of data by reaching every corner of the planet, seamlessly connecting mobile devices, and even more so with ubiquitous internet-of-things. This data needs to be processed inexpensively and energy efficiently to extract the value. Traditional architectures, although adequate for this purpose, are not optimum. Big-Data processing is mostly about information processing, rather than computing, with heavy emphasis on orchestration of efficient data movement, thus posing new design challenges. This talk will focus on: (1) the architecture of such a processing node, including CPU, covering features, size, and complexity of the core, (2) internal memory hierarchy considering recent advances in the external memory subsystem incorporating non-volatility, (3) on-die interconnect networks suitable for intra- and inter-node communication, and (4) the IO subsystem of the node to provide adequate storage bandwidth. We will discuss these topics considering recent advances in VLSI technology and its application to the Big-Data challenge.

Bio: Shekhar Borkar is an Intel Fellow, an IEEE Fellow, and Director of Extreme-scale technologies at Intel Corporation. Shekhar has been with Intel since 1981, worked on the 8051 family of microcontrollers, supercomputers, and high performance, low power digital circuit research. He has authored over 100 peer reviewed publications in conferences and journals, 56 invited papers and keynotes, four book chapters, and holds more than 60 patents. Shekhar served as the TPC chairman of VLSI Circuit Symposium in 2002, and as the conference chairman in 2004. Shekhar was an adjunct faculty at Oregon Graduate Institute, taught graduate course on VLSI design for more than 10 years. His research interests are low power, high performance digital circuits, high speed signaling, and system level optimization. Shekhar holds M.Sc. in Physics from University of Bombay in 1979, and MSEE from University of Notre Dame in 1981.

12:20 pm – 13:30 pm | Lunch
13:30 pm – 14:20 pm | Reconfigurable Computing in a Microsoft Datacenter, A. Smith, Microsoft Research

Abstract: For years FPGAs have shown huge potential to accelerate large-scale computing workloads. Yet despite the promise, FPGAs had not yet seen widespread adoption in datacenters, where their performance and energy-efficiency should be extremely attractive.
This talk will describe some of the challenges that had held FPGAs back from adoption in the datacenter, and then continue to describe Catapult, a reconfigurable fabric that meets the strict requirements of modern datacenters, while overcoming one of the greatest challenges to scaling datacenter workloads – maintaining high energy-efficiency in the face of the slowing rate of CPU performance improvements.
The Catapult reconfigurable fabric was implemented in a production environment made of 1,632 servers and FPGAs---and was used to accelerate the performance of Bing ranking by a factor of nearly 2X, while simultaneously reducing latency. This talk will summarize the motivations behind the architecture, key design choices, and the major outcomes from the evaluation.

Bio: Aaron Smith is a Principal Research Software Development Engineer at Microsoft Research and an Honorary Fellow in the School of Informatics at the University of Edinburgh. He is broadly interested in optimizing compilers, computer architecture and reconfigurable computing. Aaron received his PhD in Computer Science from UT-Austin (2009), spent one year as a visiting Associate Professor at Kyushu University in Fukuoka, Japan (2012-2013), and served as co-General Chair for the 2015 IEEE/ACM International Symposium on Code Generation and Optimization (CGO). His research has been honored with an ASPLOS best paper award and IEEE Micro Top Picks.

14:20 pm – 15:10 pm | Memories in Big Data Era, A. Kawasumi, Toshiba Corporation

Abstract: The capacity of NAND flash memory has increased by more than 1000x in the past 20 years and the DRAM modules like HBM (High Bandwidth Memory) have achieved more than 100x higher bandwidth than the early stage of DDR DRAM. These enhancements were possible not only because of the device-technology and the circuit-technique but also because of the optimization of the memory systems. And they are the important enablers for the flourish of the "Big Data" era. This presentation will overview the typical “Big Data" systems and the issues and/or requirements for the memories utilized in them. The circuit techniques and the system optimizations to fulfill the requirements will be explained. And the solutions with emerging memories (MRAM, ReRAM, …) that will enable the future "Big Data" systems will also be introduced.

Bio: Atsushi Kawasumi received his M.S. degrees in pure and applied sciences from the University of Tokyo in 1991. That same year, he joined Toshiba Semiconductor Device Engineering Laboratory in Kawasaki, Japan, since then he has been working on the research and development of high-speed and energy-efficient SRAMs. From 2002 to 2004, he moved to STI Design Center in Austin, TX where he was involved in developing the Cell/Broad Band Engine Processor. He is currently with Center for Semiconductor Research and Development where he is developing various kinds of memories. From 2009 to 2012, he served as a senior researcher at STARC in Yokohama, where he was involved in the Extremely Low Power (ELP) project. He is a program committee of ISSCC and A-SSCC.

15:10 pm – 15:25 pm | Break
15:25 pm – 16:15 pm | Role of High Bandwidth I/O for Future Performance Growth of ICT Systems, H. Tamura, Fujitsu Laboratories Ltd.

Abstract: Because device scaling is no longer improving the energy efficiency of CMOS ICs at the degree we have enjoyed over the past 60 years, it is considered that different approaches are required to support the future performance growth of computing systems. These approaches need to address the energy cost of data access/transfer, as well as the end-of-scaling that will occur sometime between 2020 and 2030. Enhancing the energy efficiency without the help of scaling will inevitably make future systems application-domain specific and data-centric, calling for cost reduction techniques in the design of such systems. In this presentation, I will firstly review the implication of scaling on the I/O performance. Subsequently, I will discuss the roles of high-bandwidth I/Os for future system-performance growth, with exemplifying the designs of very-short-reach 56-Gb/s electrical link and hybrid-integrated 25-Gb/s Si photonic transceivers.

Bio: Hirotaka Tamura received his B.S., M.S., and Ph.D. degrees in electronic engineering from Tokyo University, Tokyo, Japan, in 1977, 1979, and 1982, respectively. In 1982, he joined Fujitsu Laboratories. After becoming involved in the development of different exploratory devices, such as Josephson junction devices and high-temperature superconductor devices, he moved into the field of CMOS high-speed signaling in 1996, where he became involved in the development of a multi-channel high-speed I/O for server interconnects. Since this time, he has been working in the area of architecture- and transistor-level design for CMOS high-speed signaling circuits. He is a Fellow of the IEEE.

16:15 pm – 17:05 pm | Digital Control of Power Supplies for Server and Telecom Applications, S. Choudhury, Texas Instruments Inc.

Abstract: Digital control of power supplies is gaining increased attention due to controllers’ ability to provide increased system integration, flexible control allowing adaptation to changing system requirements, integrated system management functions, interface with digital systems, sophisticated control implementation for improved dynamic performance and efficiency.
This paper will, therefore, discuss different aspects of a digitally controlled switching power supply design. We plan to discuss in detail the following aspects:

  1. Introduction to digital power supply design, key considerations and available controllers.
  2. PWM waveform generation, open loop control to closing the loop under different control modes. Optimizing the control loop design using new tools such as, in system Software Frequency Response Analyzer (SFRA).
  3. Design and implementation of average current mode control digital Power Factor Correction (PFC) stage used in server and telecom markets. Use of harmonic compensation and notch filter to improve the PFC performance will be discussed and test results presented. Detail experimental results and measured loop gain Bode plots (using both conventional test equipment and using in system SFRA) are presented to validate the digital implementation.
  4. Design and Implementation of peak current mode control digital Phase Shifted Full Bridge (PSFB) DC-DC power supply used in server and telecom markets. Detail experimental results and measured loop gain Bode plots are presented to validate the digital implementation.

Bio: Shamim Choudhury has been with Texas Instruments Inc. since December 1997 where he currently serves as Digital Power Application Manager with C2000 Micro Controller (MCU) business unit. As a member of the system applications team, his main areas of interest have been on digital control of AC-DC & DC-DC switching power supplies, Power Factor Correction converters, UPS, Solar Inverters and motor control systems. He has published and presented multiple IEEE conference and Journal papers and TI application reports in these areas. He holds three U.S. patents on these topics. Prior to his joining TI, Shamim spent two years at Alcatel (former DSC Communications), and three years at International Game Technology, as a Design Engineer working on switch mode power supplies. He received his M.S. degree in Electrical Engineering from Texas A&M University in College Station, TX, in December 1991. He was the Technical Program Chair of the DC-DC Converter Control session at IEEE APEC 2015 Conference at Charlotte, North Carolina, USA. He is a member of IEEE Power Electronics Society.

17:05 pm – 17:10 pm | Closing Remark

Tuesday, June 16

Analog and Digital Circuit Design for IoT Swarms

Presentation Materials

Organizers / Chairs: Hideyuki Noda, Renesas Electronics Corporation and Engling Yeo, Marvell Semiconductor Inc.

10:30 am - 10:40 am | Introduction
10:40 am – 11:30 am | Overview of IoT Nodes for Physical Data Collection, P. Urard, STMicroelectronics

Abstract: Internet-of-Things enable exploration of new design spaces, opening doors to innovative applications and usages. The first generations of IoT nodes for Physical Data Collection are already available, enabling market growth. Interoperability is still poor and penetration low at this stage. We propose to overview the key features of the next generation and how the new nodes will enable on top of an IPv6 connection, an easy pairing, an easy installation, an easy debug, an easy update during life-time and a good robustness, a good quality of service even in harsh environment, a secured connection, and a very long life time. What are the impact of those features & requirements at system level and on the hardware and the firmware? We will review the trade-offs engineers have to do, and present the results achieved by the GreenNet node demonstrator.

Bio: Pascal Urard has been graduated in 1991 from ISEN (Lille, France). He joined ST Microelectronics in 1992 where he has been involved successively in test and engineering of mixed signal ASICs, SoC design, architecture and signal processing in the domain of digital communications. In 2000, he joined ST Central R&D in Crolles. He developed there both advanced signal processing IPs (digital transceivers, Turbo-codes, LDPCs, TI-ADC digital calibration) as well as design flows to increase front-end designer's productivity (Matlab-to-RTL, High-Level Synthesis tools in cooperation with CAD vendors). In 2010 he initiated the first Autonomous IPv6 Wireless Network for sensors & actuators (GreenNet), demonstrating bidirectional secured IPv6 communications over the air powered by energy harvesters. As an ST Fellow, he is now focused on ultra-low-power and energy-efficient solutions for IoT & wearable markets on the 40nm NVM and 28nm FDSOI. He has published 48 papers and has 29 granted or pending patents in the USA. He has been a member of various IEEE conferences Technical Program Committee, including ISSCC during 4 years.

11:30 am – 12:20 pm | Ultra Low Power ADCs and Analog Front-Ends, P. Harpe, Eindhoven Univeristy of Technology

Abstract: IoT applications require power-efficient data converters and analog front-ends. This presentation gives an overview of key techniques enabling the steady improvement of ADC power-efficiency in recent years. We will discuss system and architecture optimization strategies, low-power design techniques for critical building blocks, power-saving algorithms, and calibration techniques. Besides these topics, we will also discuss the design of reconfigurable ADCs, allowing context awareness and reusability. Next to introducing the generic principles, recent publications will be shown to illustrate practical implementations. The second part of the presentation explores the development of nano-power analog frontends, enabling miniature-size autonomous sensing nodes. Low-power reference generation and pre-amplification will be discussed and state-of-the-art integrated front-end systems will be highlighted.

Bio: Pieter Harpe received the M.Sc. and Ph.D. degrees from the Eindhoven University of Technology, The Netherlands. In 2008, he joined Holst Centre / imec where he worked on ultra-low-power wireless transceivers, with a main focus on ADC research and design. In April 2011, he joined Eindhoven University of Technology as assistant professor on low-power mixed-signal circuits. His main interests include power-efficient and reconfigurable data converters, signal acquisition systems and low-power analog design. He is co-organizer of the yearly workshop on Advances in Analog Circuit Design and a member of the TPC for ISSCC and ESSCIRC.

12:20 pm – 13:30 pm | Lunch
13:30 pm – 14:20 pm | Green RF: Ultra Low Power RF for the Internet of Things (IoT), A. Niknejad, University of California, Berkeley

Abstract: The Internet of Things (IoT) is fundamentally enabled by low power, low energy, and low cost nodes consisting of sensors, radio transceivers, and computation. This lecture will focus on the RF transceiver to enable communication from small coincell or thin film batteries, or perhaps by energy scavenging. Such batteries have obvious limitations in total capacity, but also have high internal resistance, which limits the peak currents available to the radio. Energy scavenging presents even bigger challenges from a peak current perspective. The IoT radio should therefore be low power and energy, which can be accomplished by deep duty cycling a relatively fast radio. RF techniques to realize low power front-end blocks will be covered, including mostly passive radios, high efficiency power amplifiers, mixers, and frequency synthesis techniques will be covered. Other approaches, such as wake-up radios and the application of MEMS technology to lower the current will also be highlighted.

Bio: Ali M. Niknejad received the Ph.D. degrees in electrical engineering from the University of California, Berkeley 2000, where he is currently a full professor and faculty director of the Berkeley Wireless Research Center (BWRC). Prof. Niknejad is an IEEE Fellow, the recipient of the 2012 ASEE Frederick Emmons Terman Award for his textbook on electromagnetics and RF integrated circuits. He was the co-recipient of the IEEE International Solid-State Circuits Conference (ISSCC) 2013 and 2010 Jack Kilby Award for Outstanding Student Papers, and the co-recipient of the Outstanding Technology Directions Paper at ISSCC 2004 for co-developing a modeling approach for devices up to 65 GHz. He is a co-founder of HMicro and the inventor of the REACH(™) technology, which has the potential to deliver robust wireless solutions to the healthcare industry. His focus areas of his research include analog, RF, mixed-signal, mm-wave circuits, device physics and compact modeling, and numerical techniques in electromagnetics. His research interests lie within the area of wireless communications and biomedical sensors and imaging.

14:20 pm – 15:10 pm | Powering the IoT - Batteries Optional, Y. K. Ramadass, Texas Instruments Inc.

Abstract: With the advent of IoT technology, a wide variety of electronic devices is expected to be deployed in often inaccessible places. Keeping these space-constrained devices powered up for their intended lifetimes is one of the primary concerns in the widespread adoption of this technology. In this talk, I will look at the energy needs of IoT devices, discuss the power delivery architecture and examine self-powered operation. The talk will delve into the basics of energy harvesting sources, storage mechanisms (batteries, supercapacitors) and the associated power management circuits needed (low-power DC/DC converters, chargers) to extend the operational lifetime of IoT devices.

Bio: Yogesh Ramadass received his B. Tech. degree from the Indian Institute of Technology, Kharagpur in 2004 and the S. M. and Ph.D. degrees in Electrical Engineering from MIT in 2006 and 2009. He is currently the director of power management R&D at Kilby Labs, Texas Instruments. Prior to his current role, he was a circuit design engineer at TI involved in the design of battery chargers, ultra-low-power DC/DC converters and high voltage drivers for wide bandgap semiconductors. Dr. Ramadass was awarded the President of India Gold Medal in 2004 and the EETimes ‘Innovator of the Year' award in 2013. He was a co-recipient of the Jack Kilby best student paper award at ISSCC 2009 and the Beatrice Winner award for editorial excellence at ISSCC 2007. He is a senior member of the IEEE and serves on the Technical Program Committee for IEEE ISSCC and IEEE ISLPED. He served as associate editor for the IEEE Journal of Solid-State Circuits special edition on ISSCC 2014.

15:10 pm – 15:25 pm | Break
15:25 pm – 16:15 pm | Low Power Microcontrollers for IoT, S. Ohtani, Renesas Electronics Corporation

Abstract: An era is about to begin in which everything is linked to networks and mutually controlled while exchanging information. Demand continues to rise dramatically for electronic products that do more and perform better while consuming less power in consumer, home, industrial, office and among others. Network technology to link one thing to another and technology to control sensors, motors and other devices are also vital. One of the important elements to meet these demands is low-power microcontrollers. In this presentation, recent technical achievements and solutions of microcontrollers as collaboration works among low-power processors (CPUs) and various IPs will be introduced.

Bio: Sugako Otani is a processor architect of embedded RX at Renesas Electronics Corporation, where she is responsible for the processor design. From 2005 to 2006, she was a Visiting Scholar at Stanford University. Her research interests include microprocessor architectures and networking. Otani has an MS in physics from Waseda University, Japan, in 1995. She is currently serving for A-SSCC Technical Program Committee and for COOL Chips Program Committee.

16:15 pm – 17:05 pm | Normally-Off Computing: Synergy of Non-Volatile Memory and Power Management, H. Nakamura, The University of Tokyo

Abstract: System level Green innovations, including Medical and Health-care Appliances, Smart City, Smart Car, and Smart Home, etc. are expected to bring us more comfortable and higher-quality human life in IoT Era. "Normally-Off Computing" is believed as one of the most promising ways to satisfy the requirement, which aggressively powers off components of computer systems when they need not to operate. Especially, high attention has been paid to Normally-Off Computing using non-volatile memories, which can make use of chances for power-off. There remain, however, a lot of problems to maximize the synergy of non-volatile memory and power management without tight collaboration of wide range of design layers including device, circuits, architecture, software, and applications. To overcome this problem, in Japan, Normally-Off Computing Project started in September 2011 under the support of NEDO (New Energy and Industrial Technology Development Organization) and METI (Japanese Minister of Economy, Trade and Industry).
In this talk, its expectation and challenges are addressed with emphasis on the synergy of non-volatile memory and power management. The current state-of-the-art results of this project are also presented.

Bio: Hiroshi Nakamura is a Professor at the Department of Information Physics and Computing in the Graduate School of Information Science and Technology at The University of Tokyo. He is also the director of Information Technology Center at The University of Tokyo.
He received the Ph.D. degree in Electrical Engineering from The University of Tokyo in 1990. His research interests include power-efficient computer architecture and VLSI design for high-performance and embedded systems. He is now leading the "Normally-Off Computing Project" supported by NEDO/METI (New Energy and Industrial Technology Development Organization / Japanese Ministry of Economy, Trade and Industry). He served IEEE ISLPED 2011 as a general chair. He is a senior member of IEEE and ACM.

17:05 pm – 17:10 pm | Closing Remark