Welcome to the 2008 Symposium on VLSI Circuits

You are cordially invited to attend the 2008 Symposium on VLSI Circuits, to be held on June 18-20th, 2008, at the Hilton Hawaiian Village in Honolulu, Hawaii. Following the rich tradition, the Circuits Symposium will follow the Symposium on VLSI Technology at the same location.

New for this year, the Circuits Symposium will overlap the Technology Symposium by two full days. The two overlap days between Technology and Circuits will allow attendees to freely choose to attend papers from either Symposium, providing a unique opportunity to learn about the latest advances in both VLSI Circuits and Technology, and to interact and exchange ideas with attendees from both Symposia.

Preceding the Symposium on June 17th, two all-day Short Courses on VLSI circuits will be held. For one registration fee, participants can attend either parallel course. The first course, focusing on new challenges facing memory and digital designers is titled “Embedded Memory Design”. The other course focuses on the growing challenges in system integration for analog and digital designers and is titled “Embedded Power Management Circuits and Systems.”

This year, the technical program committee reviewed 410 papers, selecting 84 outstanding papers for presentation. These papers disclose new developments in Memory, Analog Circuits, Data Converters, Digital Circuits and Processors, and Wireless and Wireline Communication, and represent the leading edge of VLSI circuit design. These papers are in addition to 80 papers from the Technology Symposium. Contributions come from both industry and academia, from around the world.

We have invited two distinguished speakers to describe recent advances and new challenges related to VLSI circuits, technology and applications: “Next Generation Micro-Power Systems” by Anantha Chandrakasan of Massachusetts Inst. of Technology and “Power-Efficient Heterogeneous Parallelism for Digital Convergence” by Kunio Uchiyama of Hitachi, Ltd.

To complement the formal talks, we have arranged three evening rump sessions on interesting and provocative subjects to give you an opportunity to participate in the discussions and mix with the participants who were chosen to represent contrasting opinions on the topics. The rump sessions explore: “The Future of Silicon Storage – Can Solid State Technologies Take Center Stage?”; “Photons vs. Electrons – Which will Win and When?”; “Ten Years After – Has SOI Finally Arrived?”.

Also, new for this year is the Circuits Luncheon on Friday. With a separate fee, you can enjoy an exciting and thought-provoking talk by Tom Lee of Stanford University on “The Great Transatlantic Cable and the Birth of Electrical Engineering.” It has limited space and, as with all of Tom Lee’s talks, will be very popular. So please do not wait to sign-up!

The rich technical content of the program will undoubtedly interest you, and we certainly hope that it will be a fruitful and enjoyable experience.

This booklet contains the advance program together with the on-line information and forms for the Symposium registration and hotel reservations. Please try to complete these on-line or return these forms as soon as possible. Although the on-site registration will be available at the conference, pre-registration will facilitate Symposium planning.

We look forward to meeting with you at the Symposium in Honolulu.

Katsu Nakamura

Masayuki Mizuno
Program Chair Program Co-Chair

To download a PDF of the Circuits Program - click here


Monday, June 16


Tuesday, June 17
7:30am-5:00p Registration
8:10a-5:30p Short Course
6:00p-8:00p Reception
8:00p-10:00p Technology and Circuits Joint Rump Session
Wednesday, June 18
7:30a-5:00p Registration
8:00a-9:45p Session 1 Welcome and Plenary Session I
10:00a-12:05p Session 2 High-Speed Data Converters
Technology Special Session Technology Symposium Highlights
Session 3 Parallel Processing
Session 4 Low-Power and Reconfigurable RF
3:25p-5:30p Session 5 SRAM Variability
Session 6 Wireline Signal Conditioning
7:00p-9:00p Joint Technology / Circuits Banquet
Thursday, June 19 8:00a-5:00p Registration
8:30a-10:10a Session 7 Clocking and Signaling
Session 8 Data Converters and Biomedical Circuits
9:45a-11:50a Session 9 Frequency Synthesis Components
Session 10 Multi-Standard RF
1:30p-3:10p Session 11 Processors for HDTV
Session 12 PLLs and Wireless Transceivers
3:25p-5:30p Session 13 Low Power Memory and Interface Techniques
Session 14 Power Management Circuits and Image Sensor
8:00p-10:00p Circuits Rump Session
Friday, June 20 8:00a-3:00p Registration
Session 15 Power-Aware Circuit Techniques
Session 16 60-120GHz Wireless Receivers
10:10a-11:50a Session 17 High Speed Timing Circuits
Session 18 Oversampled Data Converters
12:00p-1:15p Circuits Symposium Luncheon talk
1:30p-3:10p Session 19 Power-Aware Processing
Session 20 High Speed Transceivers
3:40p-5:05p Session 21 Cache and Embedded Memories
Session 22 Pipelined A/D Converters